Multi-layer Barrier for Interconnect Stress and Migration
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In the back end of line (BEOL) semiconductor fabrication, the continuous scaling to smaller dimensions makes it challenging to create thin barrier and seed layers that effectively inhibit copper migration and diffusion, while also reducing stress and electromigration in densely packed interconnect structures.
Innovation Solution
A multi-layer barrier layer stack is formed, comprising an adhesion barrier layer, a stress-reducing barrier layer with a TaMx alloy, and a seed layer stack with a doped seed layer, which includes a dopant to mitigate electromigration and stress migration, and a wetting layer to enhance copper fill and barrier effectiveness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the barrier and seed layers are made thin to accommodate narrow BEOL pitch geometry, then the available room for bulk copper fill is increased, but the ability to effectively inhibit copper migration and diffusion deteriorates
Solution Approach 1:
The barrier layer is divided into multiple segments: a first barrier layer (e.g., tantalum) and a second barrier layer (e.g., tungsten), creating a multi-layered barrier structure that provides enhanced copper migration inhibition while maintaining thin overall profile
Solution Approach 2:
The barrier structure uses composite materials combining different barrier metals (tantalum and tungsten) with distinct properties - tantalum provides excellent adhesion and initial barrier function, while tungsten provides superior diffusion blocking, creating a synergistic multi-functional barrier system
2Volume of moving object
If the barrier and seed layers are made thin to accommodate narrow BEOL pitch geometry, then the available room for bulk copper fill is increased, but the stress mitigation capability deteriorates
Solution Approach 1:
The seed layer is segmented into multiple functional layers including a copper seed layer and a doped copper layer, where each layer serves specific stress mitigation functions while maintaining thin overall profile
Solution Approach 2:
The dopant concentration is varied through the seed layer structure, with higher dopant concentrations in specific layers to optimize stress mitigation while maintaining electrical conductivity and enabling thin layer design
3Quantity of substance
If continuous scaling to smaller dimensions is implemented to increase device density, then the device packing efficiency is improved, but the difficulty of creating effective barrier and seed layers increases
Solution Approach 1:
The interconnect structure is segmented into distinct functional layers (first barrier, second barrier, seed layers) that can be deposited using standard sequential PVD processes, making the complex multi-functional structure achievable with existing fabrication capabilities
Solution Approach 2:
Each layer in the multi-layer barrier structure serves multiple functions - the doped seed layer simultaneously provides stress mitigation, electrical conductivity, and serves as a diffusion barrier, reducing the total number of layers needed and simplifying the overall fabrication process
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The multi-layer barrier layer stack reduces stress gradients and improves the reliability of interconnect structures by enhancing copper fill and reducing electromigration and stress migration, thereby maintaining the integrity of densely packed semiconductor devices.
Implementation Method 1
The barrier layer serves to inhibit migration or diffusion of copper into the dielectric and also to inhibit oxygen diffusion from the dielectric into the interconnect feature
Implementation Method 2
provides a dopant material for diffusion into the copper to mitigate electromigration (EM) and stress migration (SM)
Implementation Method 3
improves wettability of copper over the topography to minimize agglomeration
Data Source
AI summary
A method for forming an interconnect structure includes forming a recess in a dielectric layer of a substrate. An adhesion barrier layer is formed to line the recess. A first stress level is present across a first interface between the adhesion barrier layer and the dielectric layer. A stress-reducing barrier layer is formed over the adhesion barrier layer. The stress-reducing barrier layer reduces the first stress level to provide a second stress level, less than the first stress level, across a second interface between the adhesion barrier layer, the stress-reducing barrier layer, and the dielectric layer. The recess is filled with a fill layer.