Multi-Layer Capacitor Electrode Design for Display Devices
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As display devices evolve with smaller pixel sizes, there is a challenge in minimizing the area of individual electrodes of a capacitor while maintaining or increasing the total capacitance, which is crucial for efficient operation.
Innovation Solution
The proposed solution involves a layered structure of metal electrodes and a via layer with specific overlap areas and materials, where the area of each individual electrode is minimized, but the total capacitance is increased by optimizing the overlap areas and materials used, such as indium-tin-oxide (ITO) and other metals, and forming grooves or openings in the via layer to reduce line resistance and enhance capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the area of each individual electrode of a capacitor is minimized, then the device can be made more compact, but the total capacitance of the capacitor decreases
Solution Approach 1:
The capacitor is divided into multiple separate capacitors (first capacitor, second capacitor, third capacitor) with different electrode configurations. Each capacitor uses a portion of the available overlap area, and their capacitances are summed to achieve the total required capacitance while keeping individual electrode areas minimized.
Solution Approach 2:
The patent utilizes multiple metal layers (first metal layer, second metal layer, third metal layer, fourth metal layer) stacked vertically to create multiple capacitor structures. This vertical stacking allows the capacitor to achieve increased total capacitance without increasing the planar area of individual electrodes, as each layer contributes additional capacitance through vertical overlap.
2Device complexity
If the area of each individual electrode is minimized, then the device complexity is reduced, but the electrical conductivity and reliability of the capacitor decrease
Solution Approach 1:
The patent employs different metal materials for different layers (e.g., first metal layer, second metal layer, third metal layer, fourth metal layer) with varying electrical conductivity properties. This allows optimization where each layer's material is selected to balance electrical conductivity requirements with the minimization of individual electrode areas, thereby maintaining reliability while reducing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for a compact design with increased capacitance, improving the reliability and efficiency of the display device by reducing line resistance and enhancing electrical conductivity.
Implementation Method 1
the capacitor includes a first capacitor including a first electrode disposed in the first metal layer and a second electrode disposed in the second metal layer
Implementation Method 2
electrical conductivity of at least any one of the first through fourth electrodes is higher than electrical conductivity of the pixel electrode
Data Source
AI summary
A display device is disclosed that includes a substrate, a first metal layer disposed on the substrate, an active layer disposed on the first metal layer, a second metal layer disposed on the active layer, a third metal layer disposed on the second metal layer, a fourth metal layer disposed on the third metal layer, and a transistor and a capacitor disposed on the substrate. The transistor includes a gate electrode disposed in at least any one of the first metal layer and the second metal layer, and a drain electrode, a source electrode and an active region disposed in the active layer, The capacitor includes a first capacitor including a first electrode disposed in the first metal layer and a second electrode disposed in the second metal layer, a second capacitor including the second electrode and a third electrode disposed in the third metal layer, and a third capacitor including the third electrode and a fourth electrode disposed in the fourth metal layer.


