Multi-Layer Capacitor Structure for Narrow Frame LCD
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Solution Overview
Problem
Conventional Liquid Crystal Display (LCD) devices face challenges in achieving a narrow frame design due to the large area occupied by the row driving unit on the array substrate, which is limited by the capacitance value of the capacitor structure, as increasing the capacitance value requires larger capacitive plates without altering material or thickness.
Innovation Solution
The array substrate incorporates a capacitor structure with multiple capacitive plates formed in different layers, including a semiconductor active layer, metal layers, and dielectric layers, where projections of these plates are partially overlapped and electrically connected through via holes, allowing for a reduction in the area of each capacitive plate while maintaining a sufficiently large capacitance value.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the area of capacitive plates is increased to achieve a larger capacitance value, then the capacitance value is improved, but the area occupied by the row driving unit increases
Solution Approach 1:
The patent transitions from a conventional single-layer capacitor structure to a multi-layer stacked capacitor structure. The first and second capacitive plates are arranged in different layers (first metal layer and second metal layer respectively), with projections partially overlapping when viewed from the top. This three-dimensional arrangement increases the effective capacitance area without proportionally increasing the planar footprint, thereby resolving the contradiction between achieving high capacitance and minimizing area occupation.
Solution Approach 2:
The patent implements a nested capacitor structure where the first capacitive plate and second capacitive plate are positioned in overlapping projections. The dielectric layer is sandwiched between these nested plates, creating a compact multi-layer configuration. This nesting approach allows the capacitor to achieve larger capacitance value by utilizing vertical space and overlapping areas, rather than expanding horizontally, thus reducing the area occupied by the row driving unit.
2Reliability
If the area of capacitive plates is increased to ensure stable output signal, then the signal stability is improved, but the border width increases
Solution Approach 1:
The patent employs a multi-layer stacked capacitor configuration where capacitive plates are arranged vertically in different layers with partial overlapping projections. This three-dimensional structure increases the effective capacitance area without proportionally increasing the planar border width, allowing stable output signals to be achieved while maintaining narrow frame design requirements.
Solution Approach 2:
The nested arrangement of first and second capacitive plates in overlapping projections creates a compact capacitor structure. By nesting the plates vertically and utilizing overlapping areas, the patent achieves sufficient capacitance value for signal stability without expanding the border width, thus resolving the contradiction between signal stability and narrow frame design.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces the area occupied by the row driving unit, facilitating a narrow frame design while ensuring stable output signals, and can achieve a larger capacitance value than conventional designs, enhancing signal stability.
Implementation Method 1
the capacitance value of which is C0=ε×S/d, wherein ε the permittivity of the gate insulating layer 3, and S is an overlapped area of the first capacitive plate 2a and the second capacitive plate 4a, d is the vertical distance between the first capacitive plate 2a and the second capacitive plate 4a
Implementation Method 2
an insulating layer, and a second capacitive plate which are sequentially disposed. The first capacitive plate is parallel to the second capacitive plate
Data Source
AI summary
An array substrate is disclosed. The array substrate includes a semiconductor active layer, a gate insulation layer, a first metal layer, an interlayer dielectric layer, a second metal layer, a planarization layer and a passivation layer sequentially disposed on a base substrate; wherein the array substrate is provided with a row driving unit, including a capacitor structure; wherein the capacitor structure includes a first capacitive plate formed in the semiconductor active layer, a second capacitive plate formed in the first metal layer and a third capacitive plate formed in the second metal layer; and wherein projections of the first capacitive plate and the second capacitive plate on the base substrate are partially overlapped, projections the second capacitive plate and the third capacitive plate on the base substrate are partially overlapped and the third capacitive plate is electrically connected to the first capacitive plate through a first via hole.