Multi-layer Chip Interconnects with Segmented Metal Layers
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Solution Overview
Problem
Integrated circuits face challenges in optimizing the electrical, mechanical, and thermal performance of their interconnectivity due to the limitations of using a single material for the final metal interconnect layer, which can result in trade-offs in current capability, design rules, and compatibility issues with different external connections.
Innovation Solution
A multi-layer integrated circuit design is implemented with a stack of conductive layers of different materials, such as copper and aluminum-alloy, where contact terminals on various layers are concurrently accessible, and openings allow interconnects to extend through layers without contacting them, enabling strategic material selection for improved performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a single material is used for the final metal interconnect layer, then manufacturing is simplified, but electrical performance and compatibility with different contact types cannot be optimized simultaneously
Solution Approach 1:
The patent divides the interconnect structure into multiple metal layers (first metal layer and second metal layer) with different materials. The first metal layer uses aluminum alloy for wafer testing compatibility, while the second metal layer uses copper for flip chip bump compatibility. This segmentation allows each layer to be optimized for specific contact types, resolving the contradiction between manufacturing simplicity and electrical performance optimization.
Solution Approach 2:
The patent employs a composite interconnect structure combining different metal materials (aluminum alloy and copper) in distinct layers. Each material is selected for its specific properties: aluminum alloy for compatibility with wafer testing processes and copper for superior electrical performance in flip chip applications. This composite approach enables simultaneous optimization for multiple contact types without compromising manufacturing feasibility.
2Power
If the top metal layer is made thicker to increase current capability, then power distribution is improved, but design rules become wider and routing flexibility is reduced
Solution Approach 1:
Instead of increasing the thickness of a single top metal layer, the patent distributes current carrying capacity across multiple metal layers (first and second metal layers) in the vertical dimension. This allows the structure to achieve high current capability through cumulative cross-sectional area of conductive materials without requiring any single layer to have excessive thickness, thereby maintaining routing flexibility and avoiding overly wide design rules.
3Reliability
If different materials are used for different contact types, then electrical performance is optimized, but manufacturing complexity increases
Solution Approach 1:
The patent segments the interconnect structure into distinct metal layers, each dedicated to specific contact types. The first metal layer (aluminum alloy) serves wafer testing contacts, while the second metal layer (copper) serves flip chip bump contacts. This clear segmentation simplifies the manufacturing process by assigning specific materials to specific functions, reducing the complexity that would arise from attempting to use multiple materials throughout a single layer.
Data Source
AI summary
Representative implementations of devices and techniques provide optimized electrical performance of interconnectivity components of multi-layer integrated circuits (IC) such as chip dice, for example. Different layers of the multi-layer IC include contact terminals that may be used to connect to circuits, systems, and carriers external to the IC.