Multi-Layer Circuit Board Plating and Etching Method
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Solution Overview
Problem
Conventional methods for manufacturing multi-layer circuit boards face challenges in forming fine circuit patterns with high peel strength, are complex, and require specialized equipment, leading to increased costs and reliability issues due to air voids and low circuit pattern adhesion.
Innovation Solution
A method involving substrates with carrier and seed layers, where circuit patterns are formed by plating, aligned with a core substrate, and seed layers are etched to increase peel strength, eliminating the need for etching via holes and simplifying the manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If etching is used to form circuits on substrates, then circuit patterns can be formed, but fine circuit patterns cannot be formed and air voids are generated causing reliability deterioration
Solution Approach 1:
The patent replaces the chemical etching process with a semi-additive plating process. Instead of removing material through chemical etching, the circuit patterns are formed by depositing conductive material through plating, which enables finer pattern formation without generating air voids that compromise reliability.
Solution Approach 2:
The patent changes the fundamental parameter of circuit formation from subtractive (etching) to additive (plating). This parameter change allows for superior manufacturing precision in fine circuit patterns while eliminating the harmful air void defects inherent in etching processes.
2Manufacturing precision
If semi-additive operation is used to form circuits, then circuit patterns can be formed by plating, but peel strength of circuit patterns is low and manufacturing complexity increases
Solution Approach 1:
The patent segments the substrate into multiple layers with distinct functions: a lower substrate providing mechanical support, an adhesive layer for bonding, and an upper substrate carrying the circuit patterns. This segmentation allows each layer to be optimized independently, simplifying the overall manufacturing process while maintaining high peel strength through the adhesive layer.
Solution Approach 2:
The patent introduces an adhesive layer as an intermediary between the lower substrate and the upper substrate. This adhesive layer serves as a mediator that bonds the circuit-bearing upper substrate to the support structure, thereby enhancing peel strength without adding significant manufacturing complexity.
3Adaptability or versatility
If conventional multi-layer circuit board manufacturing is used, then substrates can be stacked, but special equipment is required and manufacturing costs increase
Solution Approach 1:
The patent designs a universal multi-layer structure where the adhesive layer and substrate configuration can be applied across different circuit board types. This universal design approach maintains the versatility of multi-layer structures while simplifying manufacturing processes and reducing equipment requirements, thereby lowering manufacturing costs.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables the production of multi-layer circuit boards with improved peel strength, reduced manufacturing complexity, and lower costs, while minimizing air void issues and enhancing reliability by embedding circuit patterns in an adhesive layer.
Implementation Method 1
etching the seed layer, wherein the seed layer is removed
Implementation Method 2
forming circuits including first circuit patterns on the upper substrate and second circuit patterns on the lower substrate by plating on the seed layer
Implementation Method 3
coupling the upper substrate, the core substrate, and the lower substrate by interposing an adhesive member
Data Source
AI summary
A method of manufacturing a multi-layer circuit layer is provided. One example method includes the steps of: preparing an upper substrate and a lower substrate, wherein each of the upper and lower substrates includes a carrier layer and a seed layer, which are detachably connected to each other; forming circuits including first circuit patterns on the upper substrate and second circuit patterns on the lower substrate by plating on the seed layer; preparing a core substrate, wherein circuit patterns comprising a conductive material are formed on the core substrate; coupling the upper substrate, the core substrate, and the lower substrate by interposing adhesive members; detaching the carrier layer from the seed layer; etching the seed layer, wherein the seed layer is removed; and electrically connecting the first circuit patterns and the second circuit patterns to the third circuit patterns, respectively.