Multi-Layer Coil Component Vertical Inductance Design
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Solution Overview
Problem
Miniaturization of thin film inductors leads to reduced coil area and turn number, resulting in decreased inductance and quality factor, making it challenging to achieve high capacity and performance.
Innovation Solution
A coil component design with multiple coil layers and a conductive via structure that maximizes the use of space, including a body with substrates, coil layers, and external electrodes, to increase the area and turn number of coils while minimizing the space occupied by conductive elements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If chip size is reduced for miniaturization, then device size is decreased, but coil area and turn number are reduced leading to decreased inductance and quality factor
Solution Approach 1:
The patent transitions from a single-layer coil structure to a multi-layer coil structure, utilizing the vertical dimension (Z-axis) to increase coil area. The coil is divided into first, second, and third layers disposed at different heights, with conductive vias connecting them, thereby increasing the effective coil area without increasing the planar footprint, resolving the contradiction between miniaturization and maintaining coil area.
Solution Approach 2:
The patent embeds multiple coil layers within the same chip footprint by stacking them vertically. The first coil layer is disposed on the upper surface of the first substrate, the second coil layer between the first and second substrates, and the third coil layer on the lower surface of the second substrate, creating a nested configuration that maximizes space utilization.
2Volume of moving object
If coil area is reduced, then chip size can be miniaturized, but direct current and alternating current resistances increase and quality factor decreases
Solution Approach 1:
By extending the coil structure into the vertical dimension with multiple layers, the patent increases the effective coil area without increasing the planar area, thereby maintaining lower resistance and quality factor while achieving chip miniaturization.
Solution Approach 2:
The patent combines multiple coil layers into a single integrated inductor structure, where the first, second, and third coil layers work together to provide the total inductance. This merging of multiple layers compensates for the reduced planar area by increasing the effective conductor cross-section, reducing resistance.
3Quantity of substance
If space is maximized for coil formation, then inductance and quality factor improve, but device complexity increases
Solution Approach 1:
The patent divides the coil into multiple discrete layers (first, second, and third coil layers) separated by substrates, with conductive vias providing connections. This segmentation allows for modular manufacturing and assembly, reducing the complexity of forming a single large-area coil while achieving the same total coil area through stacked segments.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances inductance and quality factor, enabling high-capacity performance even in miniaturized chip sizes by optimizing the coil area and magnetic flux flow.
Implementation Method 1
a conductive via passing through the first substrate and connecting the first coil layer and the second coil layer to each other
Implementation Method 2
a connection electrode disposed outside of the body and connecting the second coil layer and the third coil layer to each other
Implementation Method 3
improve the inductor performance such as the inductance (L) and the quality factor (Q) by increasing an area of the internal coil and promoting flow of the magnetic flux
Data Source
AI summary
A coil component includes a body; a first substrate disposed inside of the body, and a second substrate, disposed below the first substrate; a first coil layer disposed on an upper surface of the first substrate; a second coil layer disposed between the first substrate and the second substrate; a third coil layer disposed on a lower surface of the second substrate; a conductive via passing through the first substrate and connecting the first coil layer and the second coil layer to each other; a connection electrode disposed outside of the body and connecting the second coil layer and the third coil layer to each other; a first external electrode disposed outside of the body and connected to the first coil layer; and a second external electrode disposed outside of the body and connected to the third coil layer.