Multi-Layer Coiled Inductor with Via-Connected Series Leads
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Solution Overview
Problem
Conventional inductor elements in semiconductor devices face challenges with parasitic capacitance, particularly between vertically adjacent leads, leading to performance deterioration and increased surface area, which hampers high-frequency performance and efficiency.
Innovation Solution
The inductor element is designed with a multiple layer lead structure where coiled leads are connected in series through vias, with the current directions of vertically adjacent coiled leads being the same, resulting in a larger inter-lead capacitance between coiled leads compared to those in the same layer, reducing parasitic capacitance and allowing for higher surface area efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional inductor elements are formed with metal leads on silicon substrate, then inductance is achieved, but parasitic capacitance increases due to high conductivity and high relative dielectric constant of silicon substrate
Solution Approach 1:
The patent introduces an insulative layer as an intermediary substance between the metal leads and the silicon substrate. This mediating layer has low dielectric constant properties that reduce the parasitic capacitance formed between the conductive leads and the high-k silicon substrate, thereby improving inductor performance without sacrificing the beneficial electrical properties of silicon.
Solution Approach 2:
The patent modifies the dielectric parameter (relative dielectric constant) of the intermediate layer by selecting materials with low k-values. This parameter change in the intervening medium reduces the electric field coupling between adjacent leads and between leads and substrate, thereby reducing parasitic capacitance while maintaining the inductance function.
2Reliability
If chip surface area is increased to achieve desired inductance value, then inductance requirement is met, but manufacturing cost increases
Solution Approach 1:
The patent transitions from planar two-dimensional inductor layouts to three-dimensional vertically stacked lead configurations. By utilizing the vertical dimension with multiple lead layers separated by insulative layers, the patent achieves higher inductance values within a smaller footprint area, thereby reducing chip surface area requirements and associated manufacturing costs.
Solution Approach 2:
The patent employs composite structures combining metal leads with low-dielectric-constant insulative materials in a layered configuration. This composite arrangement enables enhanced inductance per unit area by optimizing the electromagnetic field distribution through the composite layers, achieving higher inductance values without proportionally increasing chip area.
3Stability of the object's composition
If dummy metal is added to maintain planarity in damascene process, then inter-layer insulative film planarity is retained, but parasitic capacitance increases due to reduced effective distance between inductor leads and silicon substrate
Solution Approach 1:
The patent applies different structural configurations to different regions of the device. In regions where inductor leads are present, the lead structure is designed to account for the dummy metal thickness, effectively adjusting the reference plane for capacitance calculations. This localized adaptation allows the dummy metal to serve its planarity function without uniformly increasing parasitic capacitance across the entire chip.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces unintended parasitic capacitance, improves high-frequency characteristics, and enables a more compact design with enhanced surface area efficiency, addressing the limitations of conventional inductor elements.
Implementation Method 1
the inductance of an inductor element is determined by a current flowing in a metal lead and a magnetic field created by the current
Implementation Method 2
parasitic capacitance between the metal lead forming the inductor element and the silicon substrate
Data Source
AI summary
An inductor element is formed in a multiple layer lead structure including a lead, an insulative layer that insulates leads above and below, and a via provided in the insulative layer and connecting leads above and below wherein lead layers are multiply laminated layers, characterized in that: at least a portion of at least a pair of vertically adjacent leads are coiled leads; the coiled leads are connected in series, wherein current directions of vertically adjacent coiled leads are the same by a via provided on an end portion thereof, and form a serial inductance; and an inter-lead capacitance of the vertically adjacent coiled leads is larger than an inter-lead capacitance between other coiled leads formed in the same lead layer.