Multi-Layer Display Signal Lines for Narrower LTPO Bezels
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Solution Overview
Problem
Current display technologies have wide bezels that fail to meet consumer demands for narrower bezels, particularly in Low Temperature Polycrystalline Oxide (LTPO) display panels due to the large space occupied by gate driving circuits and light-emitting control circuits.
Innovation Solution
Distribute the peripheral circuit's signal lines in at least two layers of a multi-layer metal layer, reducing the space occupied by the peripheral circuit and thus narrowing the bezel.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If the peripheral circuit is arranged in a single-layer metal structure, then the circuit layout is simple, but the bezel width becomes wide due to insufficient space utilization
Solution Approach 1:
The patent transitions from a single-layer metal structure to a multi-layer metal structure, utilizing the vertical dimension to arrange signal lines. This allows signal lines to be distributed across multiple metal layers (first metal layer, second metal layer, third metal layer), effectively reducing the horizontal space required in the peripheral region and thereby narrowing the bezel width while maintaining circuit functionality.
Solution Approach 2:
The patent segments the signal lines into different metal layers based on their functional requirements. Clock signal lines and voltage signal lines are separately routed through different layers, allowing optimized spacing and reducing interference. This segmentation enables more efficient space utilization in the peripheral region.
2Length of moving object
If signal lines are densely packed to reduce bezel width, then the bezel becomes narrower, but signal line interference increases
Solution Approach 1:
By distributing signal lines across multiple vertical layers, the patent reduces horizontal density while maintaining compact overall layout. The vertical separation between layers provides natural isolation, reducing electromagnetic interference between adjacent signal lines while still achieving narrow bezel width.
Solution Approach 2:
The patent introduces insulating layers and grounding structures as intermediaries between signal lines in different metal layers. These intermediary elements provide electrical isolation and shielding, preventing harmful interference between clock signal lines and voltage signal lines that are routed in close proximity.
Data Source
AI summary
The present disclosure provides a display apparatus, a display panel and a preparation method. The display panel includes a base substrate, a driving circuit provided on a side of the base substrate and a multi-layer metal layer: the base substrate includes a display region and a peripheral region located on a periphery of the display region; the driving circuit includes a peripheral circuit and a pixel circuit, the peripheral circuit is located at the peripheral region, the pixel circuit is located at the display region, and the peripheral circuit is connected with the pixel circuit and configured to provide a driving signal to the pixel circuit; the peripheral circuit includes a plurality of signal lines distributed in at least two metal layers.