Multi-Layer Environmental Barrier for Semiconductor Hermetic Sealing
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Solution Overview
Problem
Conventional environmental barriers for semiconductor devices, such as PECVD SiN layers, are prone to forming defects like pin holes and columnar structures, allowing moisture to penetrate and degrade the semiconductor performance, especially in high temperature and humidity environments where hermetic sealing is not always guaranteed.
Innovation Solution
A multi-layer environmental barrier composed of low-defect, low-pin hole density dielectric films formed using Plasma Enhanced Chemical Vapor Deposition (PECVD) and/or Atomic Layer Deposition (ALD) with alternating layers of different dielectric materials like silicon nitride, silicon dioxide, and polymer layers, providing a robust hermetic seal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a single-layer PECVD SiN barrier is used, then the manufacturing process is simple, but the barrier forms defects like pin holes and columnar structures that allow moisture penetration
Solution Approach 1:
The patent applies composite materials by combining multiple dielectric layers (silicon nitride, silicon dioxide, and polymer layers) with different properties to form an environmental barrier. Each layer contributes different characteristics: silicon nitride provides chemical stability, silicon dioxide provides low moisture absorption, and polymer layers provide flexibility and defect coverage. This composite structure achieves superior hermetic sealing compared to single-layer barriers while maintaining manufacturing feasibility through sequential deposition processes.
Solution Approach 2:
The patent segments the environmental barrier into multiple thin layers instead of using a single thick layer. Each layer is deposited separately with controlled thickness (e.g., 50-200 nm per layer), allowing defects in one layer to be covered by subsequent layers. This segmentation approach reduces the probability of through-defects and pin holes while maintaining overall barrier integrity and hermetic sealing performance.
2Productivity
If conventional PECVD processes are used, then the deposition is fast and simple, but the resulting film has high defect density and pin hole density
Solution Approach 1:
The patent combines multiple deposition techniques (PECVD, ALD, and spin coating) to create composite dielectric layers. PECVD provides fast deposition for silicon nitride layers, ALD provides precise control and low defect density for silicon dioxide layers, and spin coating provides uniform polymer layer deposition. This multi-method approach maintains high productivity while achieving low defect density (<10 defects/cm²) and pin hole density (<10 pin holes/cm²) through the complementary strengths of each process.
Solution Approach 2:
The patent changes deposition parameters by alternating between different deposition methods with distinct parameter sets. PECVD uses plasma-enhanced conditions for rapid silicon nitride deposition, ALD uses sequential precursor exposure for precise silicon dioxide deposition, and spin coating uses rotational speed and solution concentration control for polymer layer deposition. These parameter variations optimize both deposition speed and film quality for each layer type.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The multi-layer environmental barrier significantly reduces defect density and pin hole density to less than 10 defects and pin holes per square centimeter, effectively protecting semiconductor devices from environmental moisture and enhancing their performance and reliability.
Implementation Method 1
multiple Plasma Enhanced Chemical Vapor Deposition (PECVD) and/or Atomic Layer Deposition (ALD) layers of two or more different dielectric materials
Implementation Method 2
multiple Plasma Enhanced Chemical Vapor Deposition (PECVD) and/or Atomic Layer Deposition (ALD) layers of two or more different dielectric materials
Data Source
AI summary
Embodiments of a multi-layer environmental barrier for a semiconductor device and methods of manufacturing the same are disclosed. In one embodiment, a semiconductor device is formed on a semiconductor die. The semiconductor die includes a semiconductor body and a passivation structure on the semiconductor body. A multi-level environmental barrier is provided on the passivation structure. The multi-layer environmental barrier is a low-defect multi-layer dielectric film that hermetically seals the semiconductor device from the environment. In one embodiment, the multi-layer environmental barrier has a defect density of less than 10 defects per square centimeter (cm2). By having a low defect density, the multi-layer environmental barrier serves as a robust barrier to the environment.