Multi-Layer Etch-Stop Wiring Structures for Semiconductor Devices

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Solution Overview

Problem

As the degree of integration in semiconductor devices increases, existing wiring structures face challenges in forming conductive patterns without damaging adjacent structures, leading to issues with electrical and structural reliability due to inadequate etch-stop layers.

Innovation Solution

A multi-layered etch-stop layer is introduced, comprising a metallic dielectric material for the lower wiring and a non-metallic dielectric material for the insulation layer, with the metallic dielectric material being thicker over the wiring and the non-metallic dielectric material being thicker over the insulation layer, along with an insulating interlayer and conductive patterns extending through these layers to ensure electrical connection and protection.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a single-layer etch-stop layer is used, then the structure is simple, but the etching selectivity is insufficient causing damage to adjacent structures

Engineering Contradiction:

Improveetching selectivityVSAvoidetch-stop layer structure

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The single-layer etch-stop layer is segmented into multiple layers with different materials (first etch-stop layer with metallic dielectric material, second etch-stop layer with non-metallic dielectric material) to provide different etching selectivities for different regions, thereby protecting both the wiring and insulation layer effectively

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Different regions of the etch-stop structure are assigned different material properties: the first etch-stop layer provides metallic dielectric properties for etching selectivity against the wiring, while the second etch-stop layer provides non-metallic dielectric properties for etching selectivity against the insulation layer, achieving localized optimization of etching protection

Inventive Principle:

Principle #3Local quality

2Reliability

If the etch-stop layer thickness is increased, then the protection against etching damage is improved, but the parasitic capacitance and RC delay increase

Engineering Contradiction:

Improveprotection against etching damageVSAvoidparasitic capacitance and RC delay

Core Design Contradiction:

ReliabilityVSLoss of energy

Solution Approach 1:

The etch-stop structure uses composite materials with different dielectric properties - the metallic dielectric material in the first etch-stop layer and the non-metallic dielectric material in the second etch-stop layer - to provide adequate etching protection while maintaining lower overall parasitic capacitance compared to a single thick layer of uniform material

Inventive Principle:

Principle #40Composite materials

3Loss of energy

If the etch-stop layer thickness is reduced, then the parasitic capacitance is minimized, but the etching selectivity and protection are insufficient

Engineering Contradiction:

Improveparasitic capacitanceVSAvoidetching selectivity

Core Design Contradiction:

Loss of energyVSReliability

Solution Approach 1:

Instead of using a single thin layer that would provide insufficient protection, the etch-stop function is segmented across multiple layers, where each layer contributes to the overall etching protection while keeping individual layer thicknesses optimized to minimize parasitic capacitance

Inventive Principle:

Principle #1Segmentation

Data Source

PatentUS10229876B2Wiring structures and semiconductor devices

Publication Date: 2019.03.12 SAMSUNG ELECTRONICS CO LTD

AI summary

A wiring structure includes a substrate, a lower insulation layer on the substrate, a lower wiring in the lower insulation layer, a first etch-stop layer covering the lower wiring and including a metallic dielectric material, a second etch-stop layer on the first etch-stop layer and the lower insulation layer, an insulating interlayer on the second etch-stop layer, and a conductive pattern extending through the insulating interlayer, the second etch-stop layer and the first etch-stop layer and electrically connected to the lower wiring.