Multi-Layer Hard Mask Patterning for Precise Semiconductor Etching
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Solution Overview
Problem
The semiconductor industry faces challenges in precise control of lithography across wafers as device sizes and distances between elements are reduced, leading to issues like wiggling patterns and poor patterning results due to the limitations of conventional multi-layer stacks.
Innovation Solution
A novel multi-layer structure is formed with a semiconductive material layer over an amorphous silicon layer between two carbon layers, which prevents wiggling patterns by using a combination of etching operations and pattern transfer techniques to achieve precise patterning.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional multi-layer stacks are used for lithography patterning, then the manufacturing process is simple, but wiggling patterns and poor patterning results occur due to limitations at advanced technology nodes
Solution Approach 1:
The patent divides the patterning process into multiple sequential etching operations (first etching operation, second etching operation, third etching operation) that act on different layers (oxide layer, semiconductive material layer, conformal layer) to progressively form the final pattern. This segmentation allows precise control over pattern formation at each stage, preventing wiggling patterns while maintaining manageable process complexity through systematic decomposition of the patterning task.
2Productivity
If device sizes and distances between elements are reduced to increase device density, then greater device density and higher performance are achieved, but precise control of lithography becomes difficult leading to patterning failures
Solution Approach 1:
The patent transitions from two-dimensional planar patterning to three-dimensional multi-layer patterning by forming patterns at different vertical levels (oxide layer pattern, semiconductive material layer pattern, conformal layer pattern). This dimensional extension allows precise control of lateral dimensions through vertical layering, enabling accurate lithography control at reduced device sizes and distances while maintaining high device density.
3Manufacturing precision
If a single etching operation is used for patterning, then the process is fast and simple, but precise control over pattern dimensions and distances cannot be achieved
Solution Approach 1:
The patent performs preliminary patterning actions in sequential etching operations that prepare intermediate patterns (first patterned oxide layer, second patterned semiconductive layer, conformal layer pattern) before final pattern formation. Each preliminary action establishes precise dimensional control for subsequent operations, ensuring accurate final pattern dimensions and distances while the cumulative time investment is justified by the precision achieved at each preparatory stage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the performance of semiconductor devices and increases product yield by maintaining precise control over pattern dimensions and distances, enhancing the manufacturing process.
Implementation Method 1
A first etching operation is performed on the substrate using a comprehensive pattern of the first patterned layer and the second patterned layer
Data Source
AI summary
The present disclosure provides a method of manufacturing a semiconductor structure. A substrate is provided. A multi-layer structure is formed over the substrate, wherein the multi-layer structure includes a semiconductive material layer and an oxide layer over the semiconductive material layer. The oxide layer is patterned to form a first patterned layer. A second patterned layer is formed on the semiconductive material layer and alternately arranged with the first patterned layer. A first etching operation is performed on the substrate using a comprehensive pattern of the first patterned layer and the second patterned layer.