Multi-Layer Planar Spiral Inductor with Segmented Windings
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Solution Overview
Problem
Conventional planar spiral inductors in integrated circuits suffer from low quality factor and performance due to high resistance and parasitic capacitance, which are exacerbated by the downsizing of IC devices, leading to challenges in process uniformity and stability.
Innovation Solution
The implementation of a multi-layered inductor device configuration where first, second, and third planar spiral wirings are configured in parallel and series, with inner spiral metal wirings featuring isolated sub-metal-lines to reduce resistance and parasitic capacitance, thereby improving the quality factor and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a conventional planar spiral inductor is used, then the device is easy to integrate with low cost, but the quality factor is low due to high resistance and parasitic capacitance
Solution Approach 1:
The patent transitions from a conventional single-layer planar spiral inductor to a multi-layer stacked configuration. The inductor comprises multiple planar spiral windings arranged in different layers (first layer, second layer, third layer), where upper layers are stacked over lower layers. This three-dimensional stacking approach increases the effective inductance area without proportionally increasing the planar footprint, thereby improving the quality factor while maintaining integration compatibility.
Solution Approach 2:
The patent divides the single continuous spiral winding into multiple segmented windings distributed across different layers. Each layer contains discrete spiral windings that are electrically connected through via holes. This segmentation allows optimization of each individual winding's geometry and positioning to minimize parasitic effects while achieving the desired total inductance, thus improving quality factor.
2Area of stationary object
If the IC device is downsized, then the integration density increases, but the process uniformity and stability deteriorate
Solution Approach 1:
By stacking inductor layers vertically, the patent achieves higher integration density without further reducing the lateral dimensions. This vertical expansion maintains the process uniformity of each individual layer fabrication while increasing the overall device capacity, avoiding the process stability issues associated with extreme miniaturization.
Solution Approach 2:
The patent embeds multiple inductor layers within a compact vertical structure, where each layer is nested above the previous one. This nesting approach allows multiple functional elements to coexist in a small footprint while maintaining adequate spacing and process control for each layer, thus preserving process uniformity despite high integration density.
3Reliability
If the number of spiral windings is increased to improve inductance, then the resistance decreases, but the parasitic capacitance increases
Solution Approach 1:
The patent distributes the total number of windings across multiple vertical layers rather than concentrating them in a single plane. This spatial distribution reduces the overlapping area between adjacent windings within each layer, thereby minimizing parasitic capacitance while maintaining the total inductance through the cumulative effect of all layers.
Solution Approach 2:
The patent segments the total winding count into multiple groups, with each group forming a separate spiral winding in a different layer. This segmentation allows optimization of the winding density in each layer to balance resistance reduction with parasitic capacitance control, as the electrical connection between layers via via holes provides additional current paths without increasing lateral overlap.
Data Source
AI summary
Various embodiments provide inductor devices and fabrication methods. An exemplary inductor device can include a plurality of planar spiral wirings isolated by a dielectric layer. The planar spiral wirings can be connected by conductive pads formed over the dielectric layer and by conductive plugs formed in the dielectric layer. In one embodiment, a third planar spiral wiring can be formed over a second planar spiral wirings that is formed over a first planar spiral wiring. The third planar spiral wiring can be configured in parallel with the first third planar spiral wiring. The second planar spiral wiring can be configured in series with the first and third planar spiral wirings configured in parallel.