Multi-Layer Inner Spacers for GAA Transistor Defect Reduction
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Solution Overview
Problem
Conventional GAA transistors face challenges in inner spacer formation, leading to defects such as gate spacer damage, loss of shallow-trench isolation, and increased parasitic capacitance due to the use of low-k dielectric materials, which are prone to defects during etch back processes.
Innovation Solution
A multi-layer inner spacer feature is introduced, comprising a first inner spacer acting as an etch stop layer, a second inner spacer made of low-k dielectric material to reduce parasitic capacitance, and optionally a third spacer to further prevent defects, which are formed using specific deposition and etching processes to protect the gate and channel regions during source/drain formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If low-k dielectric material is used for inner spacer to reduce parasitic capacitance, then parasitic capacitance is reduced, but defects increase during etch back process
Solution Approach 1:
The inner spacer is divided into two distinct layers: a first inner spacer layer made of low-k dielectric material to reduce parasitic capacitance, and a second inner spacer layer made of etch-stop material to prevent defects during etch back. This segmentation allows each layer to fulfill its specific function independently, resolving the contradiction between reducing capacitance and preventing defects.
2Ease of manufacture
If etch back process is performed to form source/drain features, then source/drain features are formed, but gate spacer damage and shallow-trench isolation loss occur
Solution Approach 1:
The second inner spacer layer made of etch-stop material is deposited beforehand to protect the gate spacer and shallow-trench isolation during the subsequent etch back process. This protective layer acts as a cushion that prevents damage to critical structures while allowing the etch back to proceed for source/drain feature formation.
Solution Approach 2:
The second inner spacer layer serves as an intermediary between the etch back process and the gate spacer/shallow-trench isolation structures. It mediates the interaction by providing an etch-stop barrier that prevents direct contact between the etchant and the protected structures, thus preventing damage while allowing process completion.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The multi-layer inner spacer structure effectively reduces defects and parasitic capacitance, enhancing the reliability and performance of GAA transistors by protecting the gate and channel regions during the etch back operations and integrating low-k dielectric materials to improve electrostatic control and leakage reduction.
Implementation Method 1
a first inner spacer acting as an etch stop layer
Implementation Method 2
a second inner spacer made of low-k dielectric material to reduce parasitic capacitance
Data Source
AI summary
A semiconductor device and a method of forming the same are provided. A semiconductor device according to the present disclosure includes a first source/drain feature, a second source/drain feature, a first semiconductor channel member and a second semiconductor channel member extending between the first and second source/drain features, and a first dielectric feature and a second dielectric feature each including a first dielectric layer and a second dielectric layer different from the first dielectric layer. The first and second dielectric features are sandwiched between the first and second semiconductor channel members.