Multi-Layer Inner Spacers for Semiconductor Devices
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Solution Overview
Problem
The semiconductor industry faces challenges in achieving optimal integration density and device performance due to limitations in the design and etch resistance of inner spacers in semiconductor devices.
Innovation Solution
The use of multiple inner spacers with different etch rates and dielectric constants, comprising a high etch selectivity first dielectric layer and low k-value second and third dielectric layers, improves etch resistance and reduces effective capacitance in semiconductor devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single inner spacer layer is used, then the device structure is simple, but the etch resistance and device performance are insufficient
Solution Approach 1:
The patent employs a multi-layer inner spacer structure comprising different dielectric materials (e.g., first dielectric layer with high etch selectivity, second dielectric layer with low k-value) to achieve both high etch resistance and reduced effective capacitance. This composite approach allows each layer to contribute its specific property to the overall spacer performance, resolving the contradiction between simplicity and performance.
Solution Approach 2:
The inner spacer is divided into multiple functional layers, where each layer performs a specific function: the first dielectric layer provides etch resistance during etching processes, while the second dielectric layer reduces effective capacitance. This segmentation allows independent optimization of each function without compromising the other, addressing the technical contradiction.
2Reliability
If the inner spacer thickness is increased to improve etch resistance, then the etch resistance improves, but the effective capacitance increases
Solution Approach 1:
Different regions of the inner spacer are assigned different material properties: the first dielectric layer is optimized for etch resistance with high etch selectivity, while the second dielectric layer is optimized for low effective capacitance with low k-value. This local differentiation allows the spacer to simultaneously achieve both etch resistance and low capacitance without increasing overall thickness.
Solution Approach 2:
The patent changes the material parameters (etch selectivity and k-value) of different spacer layers to achieve the desired performance balance. By selecting materials with specific etch resistance parameters and dielectric constants, the design achieves high etch resistance while maintaining low effective capacitance, resolving the trade-off between these two parameters.
Data Source
AI summary
Improved inner spacers for semiconductor devices and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a substrate; a plurality of semiconductor channel structures over the substrate; a gate structure over the semiconductor channel structures, the gate structure extending between adjacent ones of the semiconductor channel structures; a source/drain region adjacent of the gate structure, the source/drain region contacting the semiconductor channel structures; and an inner spacer interposed between the source/drain region and the gate structure, the inner spacer including a first inner spacer layer contacting the gate structure and the source/drain region, the first inner spacer layer including silicon and nitrogen; and a second inner spacer layer contacting the first inner spacer layer and the source/drain region, the second inner spacer layer including silicon, oxygen, and nitrogen, the second inner spacer layer having a lower dielectric constant than the first inner spacer layer.