Multi-layer Interconnect with Low-Resistivity Inner Metal
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Solution Overview
Problem
As memory cells are scaled to smaller dimensions, the interconnects for memory cells, such as wordlines and bitlines, face increased resistance, limiting the current delivery to memory cells, which hinders the scaling process without significant increases in resistivity.
Innovation Solution
A multi-layer interconnect structure is introduced, where a low-resistivity inner metal layer is sandwiched between refractory outer metal layers, allowing for reduced thickness without excessive resistivity increase, using metals like aluminum and tungsten or ruthenium, and tuned based on materials and thickness to optimize performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If interconnect thickness is reduced to enable memory cell scaling, then memory device density is improved, but interconnect resistivity increases excessively
Solution Approach 1:
The patent applies composite materials by creating a multi-layer interconnect structure consisting of an inner metal layer (first material) sandwiched between two outer metal layers (second material). This composite structure combines the low resistivity of the inner layer with the protective and conductive properties of the outer layers, achieving reduced overall resistivity compared to single-material interconnects of equivalent thickness. The composite design allows thinner interconnects to maintain acceptable resistance levels while enabling continued memory cell scaling.
Solution Approach 2:
The patent implements local quality by assigning different materials to different regions of the interconnect structure. The inner metal layer uses a material optimized for low resistivity (such as copper or aluminum), while the outer layers use materials optimized for protection, adhesion, and additional conductivity (such as tungsten or ruthenium). This spatial differentiation of material properties allows the interconnect to simultaneously achieve low resistance and mechanical robustness at reduced thickness.
2Productivity
If interconnect thickness is reduced, then device scaling is enabled, but current delivery capability to memory cells deteriorates
Solution Approach 1:
The multi-layer composite interconnect structure addresses current delivery by combining materials with complementary electrical properties. The inner layer provides primary current conduction with minimal resistance, while the outer layers contribute additional conductive pathways and reduce overall resistivity. This composite approach maintains sufficient current delivery capability even as total interconnect thickness is reduced to enable device scaling.
Solution Approach 2:
The patent transitions from a single-dimensional (single-layer) interconnect to a multi-dimensional (multi-layer) structure by stacking metal layers vertically. This dimensional change increases the effective conductive cross-section without increasing the lateral footprint, thereby maintaining current delivery capability while enabling reduced overall thickness for continued device scaling.
3Ease of manufacture
If single-layer interconnect is used, then manufacturing is simpler, but resistivity increases as thickness is reduced
Solution Approach 1:
While the multi-layer composite structure increases manufacturing complexity compared to single-layer deposition, the patent optimizes the fabrication process by using sequential deposition techniques and selective etching. The resistivity benefit of the composite structure (lower resistance at reduced thickness) outweighs the moderate increase in manufacturing steps, particularly as standard semiconductor fabrication tools can handle multi-layer metal deposition.
Solution Approach 2:
The interconnect is segmented into multiple functional layers, each deposited and patterned separately. This segmentation allows for optimized material selection and thickness control for each layer's specific function (conduction, protection, adhesion), achieving superior electrical performance despite the increased number of fabrication steps compared to monolithic single-layer interconnects.
Data Source
AI summary
An apparatus comprising a substrate; and an interconnect comprising a first metal layer between and in contact with a second metal layer and a third metal layer, wherein the first metal layer has a resistivity that is lower than a resistivity of the second metal layer and a resistivity of the third metal layer.