Multi-layer interconnect with conductive protrusions for reduced pitch
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Solution Overview
Problem
The packaging of microelectronic elements, particularly semiconductor integrated circuits, faces challenges such as large area coverage, numerous external contacts, high temperature fluctuations, and the need for reduced pitch and size of contacts, which existing surface mount technologies like flip-chip interconnects struggle to address effectively, especially with the trend towards lead-free solders.
Innovation Solution
A multi-layer interconnect element is fabricated using a dielectric layer with conductive protrusions and vias to connect metal layers, allowing for efficient packaging of microelectronic elements with varying contact sizes and pitches, incorporating active or passive components and featuring plated features to connect conductive protrusions with metal layers, reducing fabrication time and material costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If flip-chip interconnect technology is used to interconnect microelectronic chips, then the interconnection can be formed quickly and reliably, but the pitch and size of contacts become larger and cannot be reduced further
Solution Approach 1:
The patent introduces a multi-layer wiring structure with conductive protrusions extending vertically from a first wiring layer through a dielectric layer to a second wiring layer. This three-dimensional arrangement allows contacts to be positioned at different heights and horizontal locations, enabling reduced contact pitch and size while maintaining reliable electrical connections. The conductive protrusions act as vertical interconnectors that resolve the spatial constraints of traditional planar flip-chip interconnects.
2Reliability
If high-lead content solder is used for solder bumps, then thermal and mechanical stresses within the package are accommodated, but the industry trend towards lead-free solder is not met
Solution Approach 1:
The patent changes the material composition parameter of the solder bumps from high-lead content to lead-free solder formulations. The multi-layer wiring structure with conductive protrusions and plated features provides enhanced mechanical support and stress distribution, compensating for the reduced ductility of lead-free solders. This allows the package to meet industry trends for lead-free solder while maintaining reliability under thermal and mechanical stresses.
3Quantity of substance
If the number of external contacts of the chip is increased, then more functionality is achieved, but the pitch and size of contacts must be reduced
Solution Approach 1:
The patent utilizes multiple wiring layers separated by a dielectric layer, with conductive protrusions extending vertically between layers. This vertical dimension allows a large number of external contacts to be distributed across multiple horizontal planes, effectively increasing the contact capacity without reducing the pitch and size of individual contacts. Each wiring layer can accommodate numerous contacts, and the total contact number is the sum across all layers.
4Area of stationary object
If processor chips with large area are packaged, then high power density and numerous contacts are accommodated, but temperature fluctuations and stress management become more difficult
Solution Approach 1:
The patent divides the packaging structure into multiple discrete wiring layers separated by a dielectric layer. Each layer can be independently designed and optimized for specific functions, including thermal management. The dielectric layer acts as a thermal barrier and stress isolation layer, segmenting the thermal pathways and reducing the propagation of temperature fluctuations across the entire large-area chip package. This segmented structure helps manage thermal stresses in high-power-density processor chips.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables efficient packaging of microelectronic elements with reduced size and pitch, accommodating different contact sizes and pitches, while reducing power consumption and electromigration, and is compatible with lead-free solders, enhancing durability and manufacturing efficiency.
Implementation Method 1
a plurality of plated features can extend through openings in the dielectric layer to conductively connect the conductive protrusions with the second metal layer
Data Source
AI summary
An interconnect element 130 can include a dielectric layer 116 having a top face 116b and a bottom face 116a remote from the top face, a first metal layer defining a plane extending along the bottom face and a second metal layer extending along the top face. One of the first or second metal layers, or both, can include a plurality of conductive traces 132, 134. A plurality of conductive protrusions 112 can extend upwardly from the plane defined by the first metal layer 102 through the dielectric layer 116. The conductive protrusions 112 can have top surfaces 126 at a first height 115 above the first metal layer 132 which may be more than 50% of a height of the dielectric layer. A plurality of conductive vias 128 can extend from the top surfaces 126 of the protrusions 112 to connect the protrusions 112 with the second metal layer.