Multi-Layer IO Pad Ring for SSD Controller Die Size Reduction
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Solution Overview
Problem
Conventional solid state device (SSD) controllers are often pad-limited due to the large number of input/output (IO) pads required to communicate with multiple flash devices, leading to increased die size and fabrication costs.
Innovation Solution
Implementing a multi-layer IO ring structure for SSD controllers, where additional IO pads are arranged in a second ring concentric with the first pad ring, utilizing unused die space and reducing the overall die size while maintaining adequate communication capabilities with multiple flash devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a large number of IO pads are used to communicate with multiple flash devices, then communication capability is improved, but die size increases
Solution Approach 1:
The patent transitions from a conventional single-layer pad arrangement to a multi-layer pad structure, utilizing the vertical dimension (different metal layers) to accommodate additional IO pads. This allows the controller to maintain adequate communication capabilities with multiple flash devices while reducing the overall die area by distributing pads across multiple layers rather than expanding the perimeter of a single layer.
Solution Approach 2:
The patent implements nested pad rings where an inner pad ring is positioned within the area encompassed by an outer pad ring. This nested arrangement allows IO pads to be organized in concentric layers, efficiently utilizing the available die space and reducing the overall footprint while maintaining the required number of communication interfaces.
2Quantity of substance
If staggered bond pad technology is used to fit more IO pads around a single perimeter ring, then pad density is improved, but effectiveness decreases when pad bodies are large or number of IO pads is large
Solution Approach 1:
The patent overcomes the limitations of staggered bond pad technology by introducing multiple layers (vertical dimension) rather than attempting to fit all pads in a single perimeter ring. This multi-layer approach provides additional space for pad bodies and allows the structure to scale effectively when the number of IO pads is large, avoiding the spatial constraints of the single-layer staggered arrangement.
3Area of stationary object
If multi-layer IO ring structure is implemented, then die size is reduced, but fabrication complexity increases
Solution Approach 1:
The patent segments the IO pad structure into multiple independent layers (first pad ring, second pad ring, etc.), each with its own set of IO pads. This segmentation allows each layer to be designed and fabricated relatively independently, and the layers can be formed using standard multi-layer metal fabrication processes, thereby managing fabrication complexity while achieving die size reduction.
Solution Approach 2:
The multi-layer pad structure uses standard semiconductor fabrication processes that are already capable of creating multiple metal layers for other circuit elements. By utilizing these existing multi-layer fabrication capabilities for the IO pad structure, the patent avoids significantly increasing fabrication complexity while achieving the benefit of reduced die size.
4Area of stationary object
If unused die space is utilized for additional IO pads, then die size is reduced, but ESD protection becomes more challenging
Solution Approach 1:
The patent segments the ESD protection into independent ESD groups for each IO pad layer. This segmentation allows ESD protection to be provided for each layer independently, managing the complexity of protecting pads distributed across multiple layers while maintaining reliable ESD protection for all IO pads, including those in the additional layers utilizing previously unused die space.
Solution Approach 2:
The patent introduces intermediate connection structures (such as vias and conductive layers) that connect the IO pads across different layers to the ESD protection circuits. These intermediary elements enable effective ESD protection for pads in the multi-layer structure, including those utilizing previously unused die space, by providing controlled pathways for ESD current dissipation.
Data Source
AI summary
Some embodiments of the disclosed subject matter include an integrated circuit. The integrated circuit includes a solid state device controller configured to control a plurality of flash memory devices, a first set of input output IO pads, coupled to the solid state device controller, arranged as a first pad ring around a perimeter of the integrated circuit, and a second set of IO pads arranged adjacent to at least one side of the first pad ring, wherein one of the second set of IO pads includes a power source node configured to receive a power supply voltage for the solid state device controller, a ground node, and a bond pad configured to receive an external signal.