Multi-layer Lithographic Target with Symmetric Sub-patterns

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Solution Overview

Problem

Conventional target systems for determining alignment and overlay errors in lithographic processes are inefficient in terms of wafer surface area usage and do not minimize proximity effects, requiring multiple targets and complex calibration across multiple layers.

Innovation Solution

A multi-level lithographic target system with symmetric sub-patterns about a common center, allowing for efficient use of the metrology tool's field of view and minimizing asymmetric proximity effects, enabling simultaneous measurement of alignment and overlay errors across multiple layers using a common metrology recipe and sampling.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of stationary object

If conventional nested box or frame targets are used on successive lithographic layers, then alignment and overlay measurement can be performed, but the targets make inefficient use of wafer surface area and require multiple targets

Engineering Contradiction:
Improvewafer surface area usageVSAvoidnumber of targets required
Core Design Contradiction:
Area of stationary objectVSDevice complexity

Solution Approach 1:

The patent combines multiple layer measurements into a single target structure. The target includes sub-patterns from multiple lithographic layers (first layer sub-patterns and second layer sub-patterns) arranged in a compact configuration, allowing simultaneous measurement of overlay between layers A-B and B-C within one target footprint, thereby reducing the number of separate targets needed and improving wafer surface area utilization.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The target design nests sub-patterns from different layers within a hierarchical structure. The first and second layer sub-patterns are positioned relative to each other within the same target field, with each layer's sub-patterns nested within the overall target geometry. This nested arrangement allows multiple layer measurements to coexist in a compact space, reducing the area required compared to conventional separate targets.

Inventive Principle:
Principle #7Nested doll (Nesting)

2Manufacturing precision

If conventional targets are used, then overlay measurement can be performed, but asymmetric proximity effects are not minimized

Engineering Contradiction:
Improveoverlay measurement accuracyVSAvoidasymmetric proximity effects
Core Design Contradiction:
Manufacturing precisionVSObject-affected harmful factors

Solution Approach 1:

The patent employs asymmetric target designs where sub-patterns from different layers are intentionally positioned at different locations within the target field. The first layer sub-patterns and second layer sub-patterns are arranged asymmetrically relative to each other, which helps minimize asymmetric proximity effects by distributing the measurement features in a configuration that reduces mutual interference and optical aberrations during metrology measurement.

Inventive Principle:
Principle #4Asymmetry

3Adaptability or versatility

If multiple targets are used for multi-layer alignment, then comprehensive coverage can be achieved, but metrology tool recipes and sampling complexity increase

Engineering Contradiction:
Improvemulti-layer coverageVSAvoidmetrology tool recipes
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The single multi-layer target serves multiple measurement functions simultaneously. It enables overlay measurement between layer A and B, between layer B and C, and potentially between other layer combinations, all within one target structure. This multi-functional design eliminates the need for separate metrology recipes for each target, simplifying the measurement process while maintaining comprehensive multi-layer coverage.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS7474401B2Multi-layer alignment and overlay target and measurement method
Publication Date: 2009.01.06 ONTO INNOVATION INC
  • US7474401B2 patent drawing
  • US7474401B2 patent drawing
  • US7474401B2 patent drawing

AI summary

A target system for determining positioning error between lithographically produced integrated circuit fields on at least one lithographic level. The target system includes a first target pattern on a lithographic field containing an integrated circuit pattern, with the first target pattern comprising a plurality of sub-patterns symmetric about a first target pattern center and at a same first distance from the first target pattern center. The target system also includes a second target pattern on a different lithographic field, with the second target pattern comprising a plurality of sub-patterns symmetric about a second target pattern center and at a same second distance from the second target pattern center. The second target pattern center is intended to be at the same location as the first target pattern center. The centers of the first and second target patterns may be determined and compared to determine positioning error between the lithographic fields.