Multi-Layer Metal Redistribution for Semiconductor Packaging
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Solution Overview
Problem
Current wafer level packaging technologies face challenges in efficiently redistributing electrical connections for complex semiconductor chips, particularly in achieving reliable and scalable manufacturing processes for multiple metallization layers with varying thicknesses and materials.
Innovation Solution
The implementation of a device with a semiconductor chip, a first metal layer of smaller thickness, a dielectric layer, and a second metal layer of significantly larger thickness, where the second metal layer is used for redistribution and external contact, allowing for efficient electrical contact and heat dissipation, and the use of a method involving a carrier, adhesive tape, encapsulation material, and sequential deposition of metal layers to create a fan-out type package.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single thin metal layer is used for redistribution, then the device complexity is reduced, but the electrical connectivity and current carrying capacity are insufficient for complex semiconductor chips
Solution Approach 1:
The redistribution layer is segmented into multiple metal layers (first metal layer and second metal layer) separated by a dielectric layer. This segmentation allows each layer to serve specific functions - the first layer provides fine-pitch interconnects while the second layer provides robust external contacts, thereby improving electrical connectivity without requiring a single complex thick layer
Solution Approach 2:
The patent transitions from a planar single-layer metallization to a three-dimensional multi-layer metallization structure. By adding the vertical dimension with stacked metal layers and dielectric spacing, the design achieves both fine-pitch routing capability and high current-carrying capacity that cannot be achieved in a single thin layer
2Reliability
If multiple thick metal layers are used for redistribution, then the electrical connectivity is improved, but the manufacturing precision and alignment requirements increase significantly
Solution Approach 1:
The patent applies local quality by making the first metal layer thinner and more precisely controlled for fine-pitch interconnects, while the second metal layer is thicker and more tolerant for external contacts. This localized differentiation of layer properties allows each layer to be optimized for its specific function while reducing overall alignment precision requirements compared to uniformly thick layers
Solution Approach 2:
The patent changes the thickness parameter of metal layers - the first metal layer has a smaller thickness optimized for fine-pitch routing, while the second metal layer has a larger thickness optimized for current carrying and mechanical robustness. This parameter differentiation relaxes alignment precision requirements by providing tolerance buffering in the thicker second layer
3Area of stationary object
If the external contact pads are made smaller, then the device area is reduced, but the packaging constraints and fabrication costs increase
Solution Approach 1:
The patent utilizes the vertical dimension with multiple metal layers to achieve area reduction. By routing signals through the first metal layer and making external contacts through the thicker second metal layer, the design can use smaller contact pads on the surface while maintaining electrical connectivity through the stacked layer structure, thereby reducing device area without increasing fabrication complexity
4Ease of manufacture
If a uniform thickness metal layer is used, then the manufacturing process is simplified, but the heat dissipation efficiency and electrical performance are compromised
Solution Approach 1:
The patent applies local quality by creating metal layers with different thicknesses - the first metal layer is thinner for fine-pitch routing where heat generation is lower, while the second metal layer is thicker specifically at external contact regions where current density and heat dissipation requirements are higher. This localized thickness variation optimizes both heat dissipation and electrical performance without requiring complete process redesign
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables increased contact area and relaxed packaging constraints, reducing fabrication costs and improving manufacturing throughput by allowing for larger external contact pads and efficient electrical connectivity, suitable for complex semiconductor chips.
Implementation Method 1
The semiconductor chip is placed over the carrier with the active main surface of the semiconductor chip facing the carrier
Implementation Method 2
A first metal layer is placed over the semiconductor chip
Implementation Method 3
A first metal layer is placed over the semiconductor chip
Implementation Method 4
A second metal layer is placed over the first metal layer, wherein the second metal layer has a thickness that is at least four times larger than the thickness of the first metal layer
Implementation Method 5
A second metal layer is placed over the first metal layer
Data Source
AI summary
A description is given of a device, including a semiconductor chip, a first metal layer laterally extending over the semiconductor chip, the first metal layer having a first thickness. A dielectric layer laterally extends over the first metal layer, and a second metal layer laterally extends over the dielectric layer, the second metal layer having a second thickness that is at least four times larger than the first thickness.