Multi-Layer Pixel Output Wiring for CMOS Image Sensors
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Solution Overview
Problem
Solid state imaging devices, such as CMOS image sensors, face image quality deterioration due to increased reading speed of pixel signals, primarily caused by increased wiring density leading to parasitic capacitance and electrical color mixing.
Innovation Solution
The implementation of a solid state imaging device with pixel output lines arranged in multiple wiring layers, where adjacent pixel output lines are alternately placed in different layers, and dummy wiring is used to uniform load capacitance, reducing parasitic capacitance and coupling effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the reading speed of pixel signals is increased, then productivity is improved, but parasitic capacitance increases causing image quality deterioration
Solution Approach 1:
The patent applies three-dimensional wiring structure by arranging pixel output lines in multiple wiring layers (first wiring layer, second wiring layer, third wiring layer) instead of a single plane. This vertical stacking reduces the horizontal density of wiring, thereby decreasing parasitic capacitance between adjacent lines while maintaining high reading speed through parallel signal paths.
Solution Approach 2:
The pixel array block is divided into multiple regions with different wiring layer assignments. Specifically, odd-numbered pixel columns connect to pixel output lines in the first wiring layer, while even-numbered pixel columns connect to pixel output lines in the second wiring layer. This segmentation distributes the wiring load across multiple layers, reducing parasitic capacitance accumulation.
2Productivity
If wiring density is increased to support higher reading speed, then productivity is improved, but electrical color mixing occurs deteriorating image quality
Solution Approach 1:
By transitioning from two-dimensional wiring layout to three-dimensional multi-layer wiring architecture, the patent physically separates pixel output lines that would otherwise be densely packed in a single layer. This spatial separation across vertical layers minimizes electromagnetic coupling between adjacent lines, preventing electrical color mixing while supporting high-speed parallel reading.
Solution Approach 2:
The patent introduces intermediate wiring layers and routing structures that act as mediators between pixel columns and pixel output lines. The third wiring layer provides additional routing paths that reduce direct coupling between signal lines, and the multi-layer structure serves as an intermediary that isolates adjacent signal lines from each other, preventing electrical color mixing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances reading speed without deteriorating image quality by minimizing parasitic capacitance and electrical color mixing, thereby preventing issues like lateral stripes.
Implementation Method 1
each of the pixels including a photodiode (PD) as a photoelectric conversion device and a plurality of transistors, and incident light is photoelectrically converted in each of the pixels
Data Source
AI summary
The present technology relates to a solid state imaging device capable of providing a solid state imaging device that does not cause deterioration of image quality due to an increase in reading speed of a pixel signal, and an imaging apparatus. In a pixel array block in which a plurality of pixels are two-dimensionally arrayed, each of the pixels including: a photoelectric conversion device; a plurality of transistors to be used for reading a signal from the photoelectric conversion device; and wiring for driving the transistors, a plurality of pixel output lines are provided for each one column of the plurality of pixels two-dimensionally arrayed, and the plurality of pixel output lines from the pixels are arranged separately in a plurality of wiring layers. The present technology can be applied to, for example, a CMOS image sensor.