Multi-Layer Redistribution Layer Impedance Control
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Solution Overview
Problem
Conventional semiconductor packaging techniques with redistribution layers face issues of high parasitic impedance, uncontrolled characteristic impedance, and increased thermal resistance, leading to signal noise, voltage drop, and reduced yield rates, especially when handling high-speed and high-frequency signals and increasing device density.
Innovation Solution
A semiconductor package design featuring multiple metal layers and passivation layers to control characteristic impedance, reduce parasitic impedance and inductance, and enhance heat dissipation, including a substrate with exposed pads, multiple metal layers electrically connected and patterned for efficient signal distribution and heat management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If long and thin traces of single-layered layout are used to redistribute power and ground signals, then the solder joint can be redistributed to periphery, two sides or any side of chip, but the characteristic impedance cannot be controlled steadily, producing noise and signal rebound
Solution Approach 1:
The patent transitions from a single-layered layout to a multi-layered structure with at least two metal layers. The first metal layer contains power traces and the second metal layer contains ground traces, creating a layered configuration that enables impedance control through vertical stacking while maintaining peripheral redistribution capability.
Solution Approach 2:
The invention uses composite structure combining multiple metal layers with different functions (power layer and ground layer) separated by dielectric material. This composite approach allows simultaneous optimization of power delivery, ground reference, and impedance control that cannot be achieved with single-layer traces.
2Adaptability or versatility
If long and thin traces are used for signal redistribution, then solder joint can be moved to periphery, but parasitic impedance and inductance increase, causing voltage drop and noise
Solution Approach 1:
By stacking metal layers vertically, the patent reduces the horizontal trace length required for power and ground connections. The vertical proximity of power and ground layers creates low-inductance return paths, reducing parasitic effects while maintaining peripheral solder joint placement capability.
Solution Approach 2:
The patent combines power and ground traces into a coupled multi-layer structure where power and ground are adjacent to each other. This merging of power and ground paths in close proximity minimizes the loop area and reduces parasitic inductance compared to separated single-layer traces.
3Adaptability or versatility
If long and thin traces are used for redistribution, then solder joint can be redistributed to periphery, but thermal resistance increases, making heat dissipation difficult and increasing chip temperature
Solution Approach 1:
The multi-layer structure provides additional vertical pathways for heat dissipation. Multiple metal layers act as thermal conduction paths from the chip to the substrate, increasing the effective heat dissipation area and reducing thermal resistance compared to single-layer traces.
Solution Approach 2:
The composite multi-layer structure with multiple metal layers and dielectric materials creates multiple parallel thermal conduction paths. The stacked configuration increases thermal conductivity from chip to substrate, improving heat dissipation while maintaining peripheral solder joint redistribution.
4Ease of manufacture
If single-layered layout with long and thin traces is used, then manufacturing is simpler, but characteristic impedance cannot be controlled for high-speed and high-frequency signals
Solution Approach 1:
The patent adds vertical dimension with multiple metal layers, enabling impedance control through layer thickness and spacing parameters. This multi-dimensional approach provides additional degrees of freedom for impedance matching while remaining compatible with standard PCB manufacturing processes.
Data Source
AI summary
The present invention relates to a semiconductor package and a method for making the same. The semiconductor package includes a substrate, a first passivation layer, a first metal layer, a second passivation layer, a second metal layer and a third metal layer. The substrate has a surface having at least one first pad and at least one second pad. The first passivation layer covers the surface of the substrate and exposes the first pad and the second pad. The first metal layer is formed on the first passivation layer and is electrically connected to the second pad. The second passivation layer is formed on the first metal layer and exposes the first pad and part of the first metal layer. The second metal layer is formed on the second passivation layer and is electrically connected to the first pad. The third metal layer is formed on the second passivation layer and is electrically connected to the first metal layer.