Multi-layer Leadless Semiconductor Package with Buildup Substrate
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Solution Overview
Problem
Existing semiconductor packages face challenges in achieving a smaller footprint with higher I/O counts while being cost-efficient, as grid array and leadframe-based packages are costly and prone to manufacturing defects, and QFN packages are limited by minimum pitch requirements.
Innovation Solution
A semiconductor package is formed with a buildup substrate having die and non-die regions, interconnect structures, and conductive elements, where a semiconductor die is electrically connected via wire bonds and encapsulated with a dielectric layer, allowing for increased I/O counts and a smaller footprint through a multi-layer buildup process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If grid array packages (BGA) are used to increase I/O connections and reduce package size, then the number of I/O connections increases and package footprint decreases, but manufacturing cost increases and vulnerability to moisture-related defects increases
Solution Approach 1:
The patent segments the package substrate into distinct die regions and non-die regions, allowing different areas to serve different functions. This segmentation enables selective placement of conductive elements and interconnect structures only where needed, reducing overall material usage and manufacturing complexity while maintaining high I/O counts.
Solution Approach 2:
The patent transitions from planar interconnect arrangements to multi-layer vertical interconnect structures. By stacking conductive elements and interconnect layers in three dimensions, the package achieves higher I/O counts without proportionally increasing footprint, while the standardized layering simplifies manufacturing processes.
2Area of stationary object
If QFN packages are used to reduce package size, then package footprint decreases, but minimum pitch between I/O connections increases
Solution Approach 1:
The patent employs multi-layer vertical interconnect structures that extend connections through the substrate thickness. This three-dimensional arrangement allows I/O connections to be stacked vertically, effectively increasing connection density without increasing the planar pitch between adjacent connections.
Solution Approach 2:
The patent nests multiple interconnect layers within the substrate structure, with conductive elements at different depths serving different I/O functions. This nested arrangement maximizes the use of available space, allowing more connections within the same footprint without requiring larger pitch between adjacent connections.
3Quantity of substance
If multi-layer buildup process is used to increase I/O counts and reduce footprint, then device performance enhances, but manufacturing process complexity increases
Solution Approach 1:
The patent divides the manufacturing process into standardized stages: forming die regions, forming non-die regions, depositing interconnect layers, and placing conductive elements. Each stage uses consistent processes regardless of the final package complexity, making the manufacturing scalable and manageable despite the multi-layer structure.
Solution Approach 2:
The patent designs the buildup process to create a universal substrate structure that can accommodate different numbers of I/O connections and various die configurations. The same interconnect layer formation and conductive element placement processes serve multiple packaging scenarios, reducing the need for specialized manufacturing steps.
Data Source
AI summary
Device and method of forming the device are disclosed. A device includes a buildup package substrate with top and bottom surfaces and a plurality of interlevel dielectric (ILD) layers with interconnect structures printed layer by layer and includes a die region and a non-die region on the top surface. A semiconductor die is disposed in the die and non-die regions of the package substrate and is electrically connected to the plurality of interconnect structures via a plurality of wire bonds. A plurality of conductive elements are disposed on the bottom surface of the package substrate and a dielectric layer encapsulates the semiconductor die, the wire bonds and the top surface of the buildup package substrate.