Multi-layer Semiconductor Package with Vertical Connectors
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Solution Overview
Problem
Conventional semiconductor packaging methods result in bulky multi-chip modules due to large package areas compared to the packaged die, limiting miniaturization and circuit density.
Innovation Solution
A semiconductor package design featuring a base substrate with a semiconductor die and an interposer substrate stacked on top, electrically coupled through vertical connectors, allowing for compact configuration with exposed interposer surfaces for additional component mounting and efficient electrical coupling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional multi-chip module packaging is used with separate microchips on a PCB substrate, then circuit density can be increased, but the module becomes bulky with large package area
Solution Approach 1:
The patent transitions from planar PCB mounting to three-dimensional vertical stacking by implementing package-on-package (PoP) configuration where semiconductor packages are stacked above each other and connected through vertical interconnects, thereby increasing circuit density without proportionally increasing package area
2Area of stationary object
If package-on-package or package-in-package configurations are used to stack die vertically, then package area is reduced, but the height of the package increases
Solution Approach 1:
The patent implements package-in-package (PiP) configuration where one semiconductor package is nested within another package structure, allowing vertical integration while minimizing the overall height by nesting components efficiently within the available vertical space
3Reliability
If an interposer is placed above a die as shown in U.S. Pat. No. 6,861,288, then electrical connection between substrates is achieved, but the package area becomes much larger than the packaged die area
Solution Approach 1:
The patent uses small-sized vertical interconnect structures (such as through-silicon vias or bump connectors) positioned only at the necessary locations where electrical connection is required between stacked packages, rather than using large interposer substrates that expand the overall package area
Data Source
AI summary
A semiconductor package comprises a base substrate with a semiconductor die mounted on a top side of the base substrate and an interposer substrate mounted on top of the die. The bottom side of the interposer substrate can be electrically coupled to the top side of the base substrate through vertical connectors. The top side of the interposer substrate is substantially exposed and comprises input/output (I/O) terminals for the mounting of additional electronic components. The base and interposer substrates can be configured with I/O terminals such that components mounted on the substrates can be electrically coupled through the vertical connectors. The base substrate also can be electrically coupled to an additional electronic component, such as a printed circuit board. Electrical connections can be “wrapped around” from the base substrate to the top of the interposer substrate. The vertical connectors can be positioned along multiple sides of the package.