Multi-Layer Stacked Capacitance Structure for High Density
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Solution Overview
Problem
Current semiconductor apparatuses have limited capacitance density, typically ranging from 7 to 10 fF/μm2, which falls short of customer demands exceeding 16 fF/μm2, necessitating innovative approaches to enhance capacitance without compromising manufacturing processes.
Innovation Solution
A multi-layer stacked capacitance structure is implemented, comprising alternating metal and insulating layers with strategically positioned pads and slits, allowing for increased capacitance density through simple manufacturing processes, including deposition and patterning of metal layers and insulating layers to expose pads for connection to outer metal layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional single-layer capacitance structure is used, then manufacturing process remains simple, but capacitance density is limited to 7-10 fF/μm2
Solution Approach 1:
The patent transitions from a conventional single-layer capacitance structure to a stacked multi-layer structure, adding the vertical dimension to increase capacitance density. By stacking multiple capacitor layers (first capacitor layer, second capacitor layer, third capacitor layer) vertically, the capacitance density increases from 7-10 fF/μm2 to over 16 fF/μm2, effectively utilizing three-dimensional space to solve the capacitance density limitation.
Solution Approach 2:
The patent implements a nested structure where multiple capacitor layers are stacked within a compact vertical space. The first capacitor layer (with first and second electrodes), second capacitor layer (with third and fourth electrodes), and third capacitor layer are nested vertically, with each layer containing electrode-insulator-electrode structures that are integrated within the overall stacked configuration, maximizing space utilization.
2Quantity of substance
If stacked MIMCAP structure is implemented to improve capacitance density, then capacitance density increases, but manufacturing process complexity increases
Solution Approach 1:
The patent merges multiple capacitor structures into a single integrated stacked MIMCAP (Metal-Insulator-Metal Capacitor) assembly. The first, second, and third capacitor layers are combined vertically with shared insulating layers and electrode structures, allowing simultaneous fabrication through coordinated deposition and patterning processes. This unified stacked structure achieves high capacitance density (over 16 fF/μm2) while maintaining manufacturing efficiency by reducing the number of discrete components and assembly steps.
3Quantity of substance
If multiple metal layers with pads are stacked, then capacitance density increases to 40-60 fF/μm2, but process complexity increases
Solution Approach 1:
The patent segments the capacitance structure into three distinct capacitor layers (first, second, and third capacitor layers), each with its own electrode pairs and insulating materials. The first capacitor layer has first and second electrodes, the second capacitor layer has third and fourth electrodes, and the third capacitor layer continues the stacked sequence. This segmentation allows independent optimization of each layer's capacitance contribution while maintaining overall structural organization, achieving total capacitance density of 40-60 fF/μm2 through cumulative effect of segmented layers.
Solution Approach 2:
The patent utilizes the vertical dimension by stacking three complete capacitor layers one above another, with each layer contributing to the total capacitance. The vertical stacking arrangement (first layer at bottom, second layer in middle, third layer at top) transforms the two-dimensional planar capacitance into three-dimensional stacked capacitance, multiplying the effective capacitance area without increasing the chip footprint, thereby achieving 40-60 fF/μm2 density.
Data Source
AI summary
A semiconductor apparatus including a stacked capacitance structure is provided. The stacked capacitance structure includes a first inner metal layer having a first pad area adjacent to an edge of the first inner metal layer, a first insulating layer disposed on the first inner metal layer and exposing the first pad area, a second inner metal layer disposed on the first insulating layer and having a second pad area adjacent to an edge of the second inner metal layer, a second insulating layer disposed on the second inner metal layer and exposing the second pad area, and a third inner metal layer covering the second inner metal layer and including at least one first slit. The first pad area and the second pad area include a plurality of pads. The first slit corresponds to the second pad area, such that the pads on the second pad area are exposed.