Multi-Layer Top Electrode Via for RRAM Contact Resistance
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Solution Overview
Problem
Resistive random-access memory (RRAM) devices face performance issues due to oxide formation between the top electrode and the top electrode via, leading to increased resistance and variability in performance across different regions of a wafer, caused by ambient exposure during fabrication.
Innovation Solution
A multi-layer top electrode configuration is implemented, comprising a first top electrode layer with a lower corrosion potential and a second top electrode layer with a higher corrosion potential, which mitigates oxide formation by reducing the resistance between the top electrode and the top electrode via, thereby improving device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single-layer top electrode is used, then the device structure is simple, but oxide formation occurs between the top electrode and top electrode via, increasing resistance
Solution Approach 1:
The top electrode is divided into multiple layers with different materials (e.g., first top electrode layer and second top electrode layer) to prevent oxide formation at the interface with the top electrode via, thereby reducing contact resistance while maintaining structural complexity at an acceptable level
Solution Approach 2:
The top electrode uses composite material structure combining different materials (such as tungsten and copper, or other metal combinations) where each layer serves a specific function: one layer provides low oxidation tendency while another provides low resistivity, solving both oxidation and resistance issues simultaneously
2Ease of manufacture
If the top electrode is exposed to ambient environment during fabrication, then the fabrication process is straightforward, but oxide formation occurs, increasing resistance and performance variability
Solution Approach 1:
The top electrode is designed with materials or structures that resist oxidation when exposed to ambient environment during fabrication, effectively creating a protective environment that prevents oxide formation and ensures consistent performance across wafers
Solution Approach 2:
The top electrode structure is pre-configured with oxidation-resistant materials or protective layers before ambient exposure occurs during fabrication, preventing oxide formation in advance rather than addressing it after exposure
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The multi-layer top electrode configuration significantly reduces resistance by minimizing oxide formation, enhancing the performance consistency of RRAM devices across different regions of a wafer, with resistance reduction ranging from 50% to 100% compared to devices without this configuration.
Implementation Method 1
the second top electrode layer having a second corrosion potential that is higher than the first corrosion potential. A top electrode via is disposed on the second top electrode layer
Data Source
AI summary
The present disclosure, in some embodiments, relates to a memory device. The memory device includes a bottom electrode disposed over a lower interconnect within a lower inter-level dielectric (ILD) layer over a substrate. A data storage structure is over the bottom electrode. A first top electrode layer is disposed over the data storage structure, and a second top electrode layer is on the first top electrode layer. The second top electrode layer is less susceptible to oxidation than the first top electrode layer. A top electrode via is over and electrically coupled to the second top electrode layer.