Multi-Layer Trace Routing for Impedance Reduction
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Solution Overview
Problem
Existing PCB designs face challenges in increasing clock speeds without compromising device reliability, as traditional methods either introduce cost and complexity or reduce reliability due to signal distortions and impedance issues.
Innovation Solution
Implementing differential trace routing on multiple layers with overlapping geometries and electrical coupling via plated through holes, which reduces impedance and maintains the original substrate design, allowing for increased clock speeds without redesigning the PCB.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional single-layer trace routing is used, then PCB design is simple, but impedance is high causing signal distortions and reliability issues at high clock speeds
Solution Approach 1:
The patent transitions from single-layer trace routing to multi-layer trace routing, utilizing the vertical dimension of PCB layers to create overlapping trace configurations. This dimensional change allows traces to be routed on different layers that overlap when viewed from the top, enabling impedance reduction through capacitive coupling between layers while maintaining a relatively simple overall PCB design structure.
Solution Approach 2:
The patent combines multiple trace layers into a unified routing configuration where traces on different layers overlap and are electrically coupled. This merging of layers creates an integrated multi-layer trace system that functions as a single low-impedance signal path, improving signal integrity while distributing the complexity across multiple layers rather than complicating a single layer.
2Reliability
If multi-layer trace routing with overlapping geometries is implemented, then impedance is reduced and signal integrity is improved, but PCB design and manufacturing complexity increases
Solution Approach 1:
The patent utilizes the vertical separation between PCB layers to implement overlapping trace geometries without increasing lateral space requirements. By routing traces on different layers that overlap when projected onto the same plane, the design achieves low-impedance coupling while maintaining standard PCB manufacturing dimensions and trace widths, avoiding the need for custom manufacturing processes.
Solution Approach 2:
The patent employs standard plated through-holes and vias that serve dual purposes: their traditional function of electrical connection between layers, and an additional function of providing capacitive coupling for impedance reduction in the overlapping trace configuration. This multi-functionality of existing PCB features avoids the need for specialized manufacturing processes.
3Speed
If clock speed is increased in traditional PCB designs, then device performance improves, but signal distortions and impedance issues reduce reliability
Solution Approach 1:
The patent uses multi-layer overlapping trace routing to create a low-impedance signal path that maintains signal integrity at high clock speeds. By distributing the trace structure across multiple layers with capacitive coupling, the design reduces impedance without requiring changes to the clock signal frequency, enabling high-speed operation while maintaining reliability.
Solution Approach 2:
The patent changes the electrical parameters of the trace routing by introducing multi-layer overlapping geometries with capacitive coupling. This parameter change reduces the characteristic impedance of the trace to better match the clock driver and memory impedance, thereby reducing reflections and signal distortions at high clock speeds without requiring clock speed reduction.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables DDR5 clock speeds to reach end-of-life speeds with improved signal integrity and reliability, reducing reflections and maintaining minimal additional design effort, while avoiding the complexity and cost of traditional methods.
Implementation Method 1
the first trace and the second trace are electrically coupled by a first and a second electrical coupling substantially perpendicular to the first layer and the second layer
Data Source
AI summary
Embodiments herein relate to systems, apparatuses, or processes directed to facilitating increased clock speeds on a substrate by lowering the impedance of traces that provide clock signals to components such as DRAM. For example, embodiments may include a substrate with a first layer and a second layer parallel to the first layer with a first trace coupled with the first layer in a routing configuration and a second trace coupled with the second layer in the routing configuration, where the routing configuration of the first trace and the second trace substantially overlap each other with respect to an axis perpendicular to the first layer and the second layer, and where the first trace and the second trace are electrically coupled by a first and a second electrical coupling perpendicular to the first layer and the second layer.