Multi-Layer Wiring Structure for Display Peripheral Area

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Solution Overview

Problem

Display devices face challenges in reducing dead space and preventing short-circuits due to fan-out wiring in the peripheral area, which limits the expansion of display area and adds defects when trying to increase functionality.

Innovation Solution

The implementation of a display device design that includes a substrate with pixel circuits, a lower metal layer, and multiple wirings in the peripheral area, where the wirings are arranged at different layers with insulating layers in between, using materials like molybdenum and titanium, and overlapping configurations to minimize dead space and prevent short-circuits.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If fan-out wirings are arranged in the peripheral area to provide various functions, then functionality is improved, but dead space increases and short-circuit defects occur

Engineering Contradiction:
ImprovefunctionalityVSAvoiddead space
Core Design Contradiction:
Adaptability or versatilityVSArea of stationary object

Solution Approach 1:

The patent applies multi-layer wiring structure where wirings are arranged in different layers (first wiring at the same layer as lower metal layer, second wiring above the first wiring with insulating layer in between). This three-dimensional arrangement allows fan-out wirings to be stacked vertically, reducing the horizontal footprint and dead space in the peripheral area while maintaining electrical connectivity for various functions.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Area of stationary object

If fan-out wirings are densely arranged to reduce dead space, then area is improved, but short-circuit defects increase

Engineering Contradiction:
Improvedead spaceVSAvoidshort-circuit defects
Core Design Contradiction:
Area of stationary objectVSReliability

Solution Approach 1:

By transitioning from two-dimensional planar arrangement to three-dimensional multi-layer stacking, the patent achieves dense wiring arrangement without increasing short-circuit risk. The vertical separation through insulating layers provides natural isolation between adjacent wirings, enabling high-density routing while maintaining electrical isolation.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent introduces insulating layers as intermediary materials between the first wiring and second wiring. These insulating layers act as mediators that provide electrical isolation and prevent short-circuits between adjacent wirings in different layers, enabling safe dense packing of fan-out wirings in the peripheral area.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Productivity

If display area is increased to improve performance, then productivity is improved, but peripheral area for wirings is reduced

Engineering Contradiction:
Improvedisplay areaVSAvoidperipheral area
Core Design Contradiction:
ProductivityVSArea of stationary object

Solution Approach 1:

The multi-layer wiring structure enables efficient utilization of the peripheral area by stacking wirings vertically. This reduces the horizontal space required for fan-out wirings, allowing the display area to be expanded while maintaining adequate space for signal routing and electrical connections in the peripheral region.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS11730030B2Display device having a first wiring at a same layer as a lower metal layer and electronic device including the same
Publication Date: 2023.08.15 SAMSUNG DISPLAY CO LTD
  • US11730030B2 patent drawing
  • US11730030B2 patent drawing
  • US11730030B2 patent drawing

AI summary

A display device includes: pixel circuits in a display area, the pixel circuits each comprising a thin film transistor and a capacitor, the thin film transistor including a semiconductor layer and a gate electrode on the substrate and the capacitor including a first capacitor plate and a second capacitor plate; signal lines electrically connected to the pixel circuits, the signal lines passing through the display area; a lower metal layer between the substrate and at least one of the pixel circuits; a pad portion in the peripheral area; and a plurality of wirings in the peripheral area, the plurality of wirings electrically connecting the pad portion to the signal lines, wherein the plurality of wirings further comprise: a first wiring at a same layer as the lower metal layer; and a second wiring above the first wiring with a first insulating layer between the first wiring and the second wiring.