Multi-Layer Wiring Structure for 3D NAND Memory
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Solution Overview
Problem
In three-dimensional NAND-type flash memory, the existing multi-layer wiring structures face challenges in reducing the chip area and improving manufacturing yield due to misalignment issues in photolithography and the need for large hookup areas to maintain withstand voltage margins, leading to increased complexity and defects.
Innovation Solution
A multi-layer wiring structure is developed with alternately layered conductors and insulators, featuring contact plugs with spacers and support pillars that allow for reduced chip area and improved manufacturing accuracy by eliminating stepwise gate electrodes and optimizing contact hole processing, enabling smaller hookup areas and enhanced yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If photolithography is used to form contact holes through multi-layer wiring structures, then electrical connections can be established, but misalignment occurs leading to manufacturing defects
Solution Approach 1:
The patent introduces an intermediary etching process using a sacrificial layer (e.g., silicon oxide or silicon nitride) that is selectively removed to form contact holes. This sacrificial layer acts as a mediator that enables precise contact hole formation without requiring direct photolithography alignment through multiple conductor layers, thereby eliminating misalignment issues and improving manufacturing yield
Solution Approach 2:
The patent applies preliminary action by forming the sacrificial layer and contact hole pattern before depositing the upper conductor layers. The contact holes are pre-formed through the insulating layers using the sacrificial layer as an etch stop, ensuring precise alignment is achieved before the complex multi-layer wiring is assembled, thus preventing misalignment defects
2Reliability
If large hookup areas are used to maintain withstand voltage margins, then electrical reliability is improved, but chip area increases
Solution Approach 1:
The patent transitions from planar voltage isolation to three-dimensional field control by strategically positioning conductors and insulators in multiple layers. The withstand voltage margin is achieved through vertical field management and layered insulation structures rather than increasing horizontal hookup area, enabling compact chip design while maintaining electrical reliability
Solution Approach 2:
The patent applies local quality by providing enhanced insulation and voltage isolation only in critical regions where high voltage margins are required, rather than uniformly increasing hookup area across the entire chip. Different regions of the chip have different insulation densities and layer configurations optimized for their specific voltage requirements, reducing overall chip area while maintaining reliability
3Ease of manufacture
If stepwise gate electrodes are used in multi-layer wiring, then electrical connections can be formed, but manufacturing complexity increases
Solution Approach 1:
The patent extracts and removes the complex stepwise gate electrode structure from the multi-layer wiring design. Instead of forming electrodes in multiple stepped layers, the invention uses planar conductor layers with contact holes penetrating through insulating layers to establish connections, significantly simplifying the manufacturing process while maintaining electrical functionality
Solution Approach 2:
The patent segments the wiring structure into distinct functional layers: planar conductor layers for signal transmission, insulating layers for isolation, and contact holes for vertical connections. This segmentation eliminates the need for complex stepwise gate electrodes by separating the functions of horizontal conduction and vertical connection into different structural elements, reducing manufacturing complexity
Data Source
AI summary
According to one embodiment, a multi-layer wiring structure includes a first multi-layer section, first contact plugs, and pillars. First conductors and first insulators are alternately layered in the first multi-layer section. The multi-layer section includes a first area that includes memory cells, and a second area different from the first area. The first contact plugs are formed in the first holes extending from an uppermost layer of the first multi-layer section respectively to the first conductors in the second area, side surfaces of the first contact plugs being covered with first insulating films. The pillars are formed of second insulators and passing through the first multi-layer section in a layered direction in the second area.