Multi-Layer Wiring Structure for Semiconductor Package Warpage Reduction

Solution Overview

Problem

The increasing number of input/output (I/O) connections in semiconductor chips leads to warpage issues in semiconductor device packages, affecting the yield of packaging substrates as the size of the packaging substrate grows, resulting in low manufacturing yield and high costs.

Innovation Solution

A multi-layer wiring structure is developed, comprising units with circuit and dielectric layers, insulation walls, and redistribution layers, which are stacked and encapsulated to form a substrate with improved yield and cost efficiency, using a method that includes forming redistribution layers on units and stacking them to create a panel of wiring structures.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If the size of the packaging substrate is increased to accommodate more I/O connections, then the number of I/O connections is improved, but warpage of the semiconductor chip package becomes more severe

Engineering Contradiction:

Improvenumber of I/O connectionsVSAvoidwarpage of semiconductor chip package

Core Design Contradiction:

Quantity of substanceVSStability of the object's composition

Solution Approach 1:

The substrate is divided into multiple smaller units (first units, second units, third units) that are stacked vertically. Each unit contains a portion of the circuit layers and dielectric layers. This segmentation allows the substrate to accommodate more I/O connections through vertical stacking while each individual unit maintains a manageable size that reduces warpage issues.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent transitions from a planar two-dimensional substrate layout to a three-dimensional stacked architecture. By adding the vertical dimension with multiple layers of units separated by redistribution layers, the substrate can handle increased I/O connections without proportionally increasing the footprint area, thereby maintaining stability and reducing warpage.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Quantity of substance

If the size of the packaging substrate is increased to accommodate more I/O connections, then the number of I/O connections is improved, but manufacturing yield decreases

Engineering Contradiction:

Improvenumber of I/O connectionsVSAvoidmanufacturing yield

Core Design Contradiction:

Quantity of substanceVSProductivity

Solution Approach 1:

The substrate is divided into multiple smaller units (first units, second units, third units) that are stacked vertically. Each unit contains a portion of the circuit layers and dielectric layers. This segmentation allows the substrate to accommodate more I/O connections through vertical stacking while each individual unit maintains a manageable size that reduces warpage issues.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent transitions from a planar two-dimensional substrate layout to a three-dimensional stacked architecture. By adding the vertical dimension with multiple layers of units separated by redistribution layers, the substrate can handle increased I/O connections without proportionally increasing the footprint area, thereby maintaining stability and reducing warpage.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

3Quantity of substance

If the size of the packaging substrate is increased to accommodate more I/O connections, then the number of I/O connections is improved, but manufacturing cost increases

Engineering Contradiction:

Improvenumber of I/O connectionsVSAvoidmanufacturing cost

Core Design Contradiction:

Quantity of substanceVSEase of manufacture

Solution Approach 1:

Multiple units with circuit layers and dielectric layers are merged vertically into a single stacked structure. The redistribution layers serve as common interconnection structures that electrically connect corresponding pads across different units. This merging approach allows the substrate to provide more I/O connections while sharing common structural elements, thereby reducing per-connection manufacturing cost.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The patent transitions from a planar two-dimensional substrate layout to a three-dimensional stacked architecture. By adding the vertical dimension with multiple layers of units separated by redistribution layers, the substrate can handle increased I/O connections without proportionally increasing the footprint area, thereby maintaining stability and reducing warpage.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS10796928B1Wiring structure and method for manufacturing the same

Publication Date: 2020.10.06 ADVANCED SEMICON ENG INC

AI summary

A wiring structure includes a first unit, a second unit, a first insulation wall, a first redistribution layer and a third unit. The first unit is disposed at a first elevation and having a first circuit layer and a first dielectric layer surrounding the first circuit layer. The second unit is disposed at the first elevation and having a second circuit layer and a second dielectric layer surrounding the second circuit layer. The first insulation wall is disposed between the first unit and the second unit. The first redistribution layer is disposed on the first unit and the second unit, and electrically connected between the first unit and the second unit. The third unit is disposed on the first redistribution layer and having a third circuit layer and a third dielectric layer surrounding the third circuit layer.