Multi-layered Capacitor Vertical Stacking for Chip Area Utilization
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Solution Overview
Problem
Conventional multi-layer capacitors in semiconductor chips are inefficient in using space and area, leading to dead space and reduced integration due to design constraints that prohibit active or passive devices in above or below layers, limiting capacitance density and increasing chip size.
Innovation Solution
A multi-layered capacitor design that includes a first MIM-type capacitive element with a second capacitive element, such as MOM, POP, or MOS-CAP, arranged either above or below the first element, allowing for efficient use of space by stacking capacitive elements on the same or adjacent layers, with electrical connections between them.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional MIM capacitor structure is used with design rules prohibiting devices in above or below layers, then the capacitor provides lower resistance and higher density of capacitance, but the above and below layers are not used efficiently, creating dead space in the semiconductor chip
Solution Approach 1:
The patent transitions from a single-layer capacitor design to a multi-layered structure where capacitive elements are stacked vertically across multiple layers. The first capacitive element is formed on a first layer and the second capacitive element is formed on a second layer adjacent to the first layer, utilizing the vertical dimension to increase capacitance density without expanding chip area.
Solution Approach 2:
The patent implements a nested structure where the second capacitive element is positioned within the vertical space above or below the first capacitive element. The conductive plates and insulating layers are arranged in a nested configuration across adjacent layers, effectively utilizing the three-dimensional space that would otherwise be dead space in conventional designs.
2Quantity of substance
If more capacitance is provided in a conventional capacitor structure, then the capacitance density increases, but more dead space is created in the semiconductor chip
Solution Approach 1:
The patent resolves this contradiction by moving from two-dimensional planar expansion to three-dimensional vertical stacking. Multiple capacitive elements are arranged in the vertical direction across adjacent layers, allowing high capacitance to be achieved within a compact chip volume by utilizing the vertical dimension rather than expanding horizontally.
Solution Approach 2:
The patent divides the capacitor structure into multiple discrete capacitive elements (first capacitive element and second capacitive element) formed on separate adjacent layers. Each capacitive element consists of conductive plates and insulating layers segmented across different layers, allowing independent optimization of each element while achieving high total capacitance in a compact volume.
Data Source
AI summary
According to the present invention, a multi-layered capacitor includes a first capacitive element having a first conductor plate formed on a first layer, a second conductor plate formed on a second layer and an insulator arranged between the first and second conductor plates; and a second capacitive element which is arranged just on a layer above or below the first capacitive element.