Multi-layered Conductive Base for Semiconductor Package Thermal Stress
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Solution Overview
Problem
Ceramic surface mount device (SMD) packages face thermal stress and cracking due to coefficient of thermal expansion (CTE) mismatch with printed circuit boards (PCBs), leading to hermeticity loss and damage to semiconductor devices.
Innovation Solution
A semiconductor package with a multi-layered conductive base, featuring a terminal pad with a CTE closely matched to the ceramic case and a mounting tab with a CTE between the ceramic case and the PCB, reducing mechanical and thermal stress through a gradual CTE change, thereby minimizing cracking and enhancing structural integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a ceramic SMD package is mounted onto a PCB with a large CTE, then the package can be used with various PCB materials, but the CTE mismatch introduces thermal stress that causes cracking and hermeticity loss
Solution Approach 1:
The base is divided into multiple layers with different materials, each layer having different CTE properties. The first base layer (ceramic) matches the ceramic case CTE, while the second base layer (metal) matches the PCB CTE, creating a segmented structure that bridges the CTE gap between ceramic and PCB
Solution Approach 2:
The base uses a composite structure combining ceramic material in the first layer and metal material in the second layer. This composite base leverages the advantages of both materials: ceramic provides thermal stability and low CTE matching the case, while metal provides higher CTE matching the PCB and mechanical flexibility
2Ease of manufacture
If a single-material base is used, then the manufacturing process is simple, but the CTE mismatch with both ceramic case and PCB causes thermal stress and cracking
Solution Approach 1:
The base is segmented into two distinct layers with different materials optimized for different functions: the first ceramic layer for thermal matching with the case, and the second metal layer for mechanical matching with the PCB. This segmentation allows each layer to be optimized independently while working together as a unified base structure
Solution Approach 2:
Different regions of the base have different material properties tailored to their specific functions. The first layer near the ceramic case has low CTE for thermal stability, while the second layer near the PCB has high CTE for mechanical compliance. Each local region's material quality is optimized for its specific environmental conditions
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces thermal and mechanical stress, preventing cracking and ensuring reliable hermetic sealing and performance of the semiconductor package across various PCB materials, improving its structural integrity and operational reliability.
Implementation Method 1
the coefficient of thermal expansion (CTE) incompatibility of the SMD package and the PCB materials... a CTE mismatch between the ceramic SMD package and the PCB may introduce thermal stress to the ceramic SMD package
Data Source
AI summary
A semiconductor package for mounting to a printed circuit board (PCB) includes a semiconductor die in a ceramic case, a conductive base coupled to the semiconductor die at a top surface of the conductive base, where the conductive base includes a first layer having a first coefficient of thermal expansion (CTE), and a second layer having at least one mounting tab and a second CTE. The conductive base is configured to reduce thermal stress in the ceramic case, where the first CTE is equal to or slightly different than a CTE of the ceramic case, the second CTE is greater than the first CTE, and a CTE of the PCB is greater than or equal to the second CTE. The conductive base is configured to electrically couple a power electrode of the semiconductor die to the PCB.


