Multi-Length Gate Electrode Layout for Sub-2 Nm Gate Control
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Solution Overview
Problem
Current methods for modulating gate length in integrated circuit (IC) fabrication, such as self-aligned double patterning (SADP), face challenges including complexity, minimum thickness limitations, and variations in source-drain opening widths, which affect epitaxial growth and transistor performance.
Innovation Solution
The implementation of a dry clean-based spacer thinning process to achieve multi-length gate electrodes by controlling the etch selectivity and using block patterning to determine etch areas, allowing for precise modulation of gate length without causing variations in source-drain trench width.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If self-aligned double patterning (SADP) is used to modulate gate length, then gate length control is achieved, but process complexity increases and minimum thickness limitations occur
Solution Approach 1:
The patent extracts the gate length modulation function from the complex SADP process by introducing a separate mandrel structure. The mandrel serves as a standalone template that defines gate length through its dimensions, allowing gate length control without requiring the full SADP process complexity. The mandrel is formed independently and then used to pattern the gate electrode, separating the length control function from the patterning complexity.
Solution Approach 2:
The patent introduces a mandrel structure as an intermediary element between the patterning process and the final gate electrode. This mandrel acts as a mediator that transfers the desired gate length dimension to the gate electrode without requiring direct complex patterning of the gate material itself. The mandrel facilitates precise length control while simplifying the overall process by decoupling length definition from electrode formation.
2Manufacturing precision
If SADP spacer thickness is reduced to achieve smaller gate lengths, then gate length modulation is improved, but source-drain opening width variations increase
Solution Approach 1:
The patent segments the patterning process into distinct functions: the mandrel defines gate length independently, while the subsequent patterning steps define source-drain openings separately. This segmentation allows each dimension to be controlled independently without the coupling that causes variations in SADP. The mandrel's dimensions control gate length, while separate etching and deposition steps control opening widths, eliminating the trade-off between these parameters.
Solution Approach 2:
The patent performs preliminary action by forming the mandrel structure with pre-defined dimensions before the gate electrode patterning. The mandrel is created with precise length and width specifications that predetermined the final gate dimensions. This preliminary structuring allows subsequent steps to follow the mandrel's geometry without introducing variations, ensuring consistent source-drain opening widths while achieving the desired gate length modulation.
3Adaptability or versatility
If additional thin spacer deposition is used to increase gate length, then gate length range is expanded, but minimum thickness gap limitations are encountered
Solution Approach 1:
The patent changes the fundamental parameter for gate length definition from spacer thickness to mandrel dimensions. Instead of relying on the minimum thickness of deposited spacers, the gate length is defined by the mandrel's length parameter, which can be varied over a wider range without being constrained by deposition thickness limits. This parameter change enables expanded gate length range while avoiding the minimum thickness gap limitation inherent in spacer-based approaches.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables more precise control of gate length (below 2 nm) without complicating the SADP process, improving variable control and reducing variations in transistor performance.
Implementation Method 1
controlling the etch selectivity and using block patterning to determine etch areas
Data Source
AI summary
An IC device includes a gate electrode having multiple lengths. The length of a first portion of the gate electrode, which is over a channel region in a semiconductor structure, may be longer (e.g., about 0.5-3 nm longer) than the length of a second portion of the gate electrode, which is over a channel region in another semiconductor structure. The pitches at the two portions of the gate electrode may be the same or substantially similar. The lengths of the gate electrode can be differentiated by using dry clean based removal of a dielectric material surrounding the semiconductor structures. A larger amount of the dielectric material may be removed at a first region than a second region so that the gap at the first region can be longer than the gap at the second region. A conductive material may be provided to fill the gaps to form the gate electrode.