Multi-Level Buffer for ECC Read Throughput
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Solution Overview
Problem
High-density memory devices with built-in error correcting codes (ECCs) face reduced read throughput due to the need to complete error correction before moving data from the cache to the data path, which limits the simultaneous processing of multiple data pages.
Innovation Solution
A multi-level buffer structure is introduced between the memory array and the input/output data path, allowing for time-overlapping operations where error correction is applied to one page while data from another page is moved to the cache, enabling simultaneous processing and movement of multiple data pages without waiting for error correction to complete.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error correction is applied to data before moving it from cache to data path, then data reliability is improved, but read throughput deteriorates
Solution Approach 1:
The buffer structure is segmented into multiple levels (first buffer, second buffer, third buffer) that can operate independently. Data pages are divided and processed across different buffer levels, allowing error correction on one page to occur simultaneously with data movement of other pages, thus resolving the contradiction between ensuring data reliability and maintaining high read throughput
Solution Approach 2:
Error correction is applied to data pages in advance while they are being transferred through the buffer structure, before the corrected data needs to be output to the data path. This preliminary action allows the ECC logic to process multiple pages in parallel, improving read throughput without compromising data reliability
2Productivity
If a single buffer structure is used, then device complexity is reduced, but read throughput deteriorates due to sequential processing
Solution Approach 1:
The buffer structure transitions from a single-level to a multi-level hierarchical arrangement (first buffer connected to second buffer connected to third buffer). This dimensional change in the buffer architecture enables parallel data flow paths, allowing multiple data pages to be processed simultaneously and significantly improving read throughput despite the increased structural complexity
Data Source
AI summary
A device includes a memory array storing data and error correcting codes ECCs corresponding to the data, and a multi-level buffer structure between the memory array and an input/output data path. The memory array includes a plurality of data lines for page mode operations. The buffer structure includes a first buffer having storage cells connected to respective data lines in the plurality of data lines for a page of data, a second buffer coupled to the storage cells in the first buffer for storing at least one page of data, and a third buffer coupled to the second buffer and to the input/output data path. The device includes logic coupled to the multi-level buffer to perform a logical process over pages of data during movement between the memory array and the input/output path through the multi-level buffer for at least one of page read and page write operations.