Multi-Level Cache Compression for Pixel Data
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Solution Overview
Problem
Current graphics processing technologies face inefficiencies in compressing pixel write data generated by compute tasks, particularly due to arbitrary writes and the challenge of handling incomplete blocks, which affects memory bandwidth and power consumption.
Innovation Solution
Implementing a multi-level compression circuitry that accumulates and compresses pixel data across different cache levels, using programmable shaders and compression/pack circuitry to manage metadata and ensure full accumulation before writing to memory, thereby optimizing compression ratios and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If compression is applied to pixel write data from compute tasks, then memory bandwidth is reduced and power consumption decreases, but compression efficiency deteriorates due to arbitrary writes and incomplete blocks
Solution Approach 1:
The patent segments the compression process into multiple independent compression circuits, each handling specific blocks of pixel data. This allows parallel processing of different block segments, improving overall compression throughput while maintaining efficiency even when individual blocks are incomplete. The segmentation enables the system to process available data in each block independently rather than waiting for complete blocks.
Solution Approach 2:
The patent implements preliminary accumulation of pixel data in cache memory before compression. The system accumulates pixel writes in cache circuits and prepares them for compression in advance, allowing the compression circuits to process data as soon as sufficient data is available. This preliminary action reduces idle time in the compression pipeline and improves overall compression efficiency for arbitrary write patterns.
2Loss of information
If multi-level caching is implemented to improve compression, then compression ratios improve, but device complexity increases
Solution Approach 1:
The patent implements a nested cache hierarchy with multiple levels of caching (e.g., L1 cache, L2 cache) where smaller caches are nested within larger ones. This nested structure allows data to be cached at multiple granularities, improving compression ratios by accumulating more complete blocks at higher cache levels while managing complexity through hierarchical organization rather than monolithic complex structures.
Solution Approach 2:
The patent adds the temporal dimension to compression by implementing multi-level caching across time. Instead of single-pass compression, the system caches data across multiple cache levels and compression passes, allowing accumulation of data over time to achieve better compression ratios. This transforms the compression process from a single-dimension operation to a multi-dimensional process involving multiple cache levels and time stages.
Data Source
AI summary
Techniques are disclosed relating to compression of data stored at different cache levels. In some embodiments, a memory system implements a storage hierarchy that includes first cache circuitry and second cache circuitry at different levels of the hierarchy. Processor circuitry generates write data to be written to the memory system. In some embodiments, first compression circuitry is configured to compress a first block of write data in response to full accumulation of the first block in the first cache circuitry and second compression circuitry is configured to compress a second block of write data in response to full accumulation of the second block in the second cache circuitry. Write circuitry may write the first and second compressed blocks of data in a single combined write to a higher level in the storage hierarchy.