Multi-Level Cache Security With Shadow Tag Coherency
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Solution Overview
Problem
Increasingly complex memory architectures face scalability challenges when adding powerful CPUs, particularly when multiple CPUs share a common address space, leading to increased processing demands and latency due to cache coherency and security requirements.
Innovation Solution
Implementing a multi-level cache system with shadow cache tag storage and memory controllers to maintain coherency and security, using secure codes to manage access to data subsets, and employing a hierarchical memory architecture with multiple levels of caching and controllers to optimize data transfer and security.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If multiple CPUs share a common address space with multi-level cache, then processing power and functionality are improved, but cache coherency maintenance complexity and processing demands increase
Solution Approach 1:
The cache tag storage is segmented into multiple independent sets, each set associated with specific CPUs or security contexts. This segmentation allows each CPU to access only its designated cache tags, reducing the complexity of maintaining coherency across all CPUs while preserving multi-CPU processing power.
Solution Approach 2:
A cache controller acts as an intermediary between multiple CPUs and the cache memory system. The controller manages tag comparisons, security code verification, and coherency maintenance, offloading these complex tasks from individual CPUs and reducing overall system complexity.
2Reliability
If cache is configured to protect certain areas from unauthorized CPU access, then data security is improved, but access latency increases due to additional verification steps
Solution Approach 1:
Security codes and context information are pre-stored in the cache tags alongside data addresses. When a CPU requests access, the pre-stored security information is immediately compared with the requesting CPU's context, enabling rapid security verification without adding significant latency while maintaining strong access protection.
3Measurement precision
If secure codes are stored in cache tags for each data subset, then access control precision is improved, but memory usage and tag storage complexity increase
Solution Approach 1:
The cache tag structure is designed to serve multiple functions simultaneously: storing address information for data location, security codes for access control, and context identifiers for CPU identification. This multi-functionality enables precise access control without requiring separate storage structures, thereby avoiding increased memory usage.
Data Source
AI summary
An example system includes first and second level caches, each including a corresponding memory, a corresponding memory controller, and corresponding cache tag storage. The second level cache also includes shadow cache tag storage that includes tags for use by the second level memory controller for maintaining coherency between the first level memory and the second level memory. In an example, the first level cache tag storage includes a main cache tag storage and a victim cache tag storage, and the shadow cache tag storage includes a shadow main cache tag storage and a shadow victim cache tag storage. The shadow main cache tag storage contains tags mapped to respective tags in the main cache tag storage, and the shadow victim cache tag storage contains tags mapped to respective tags in victim cache tag storage.