Multi-level Circuit Topology Reducing Capacitor Count and Voltage Stress
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing multi-level power electronics circuits face complexity due to high voltage withstand requirements for semiconductor switches and a large number of bus capacitors, leading to increased design complexity and component stress.
Innovation Solution
A five-level and seven-level circuit topology is introduced, featuring two groups of bus capacitors and switching transistor branches with reduced voltage withstand requirements, utilizing coupled inductors and half bridges to achieve efficient voltage regulation and level output, while simplifying circuit design by reducing the number of bus capacitor groups.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a four-level or five-level multi-level technology is used to reduce circuit loss and improve efficiency, then work efficiency is significantly improved, but the circuit topology becomes complex and semiconductor devices require high voltage withstand performance
Solution Approach 1:
The patent segments the multi-level circuit into multiple three-level circuit units (first three-level circuit unit, second three-level circuit unit, third three-level circuit unit, fourth three-level circuit unit) that are connected in parallel. Each unit handles a portion of the power conversion independently, achieving five-level or seven-level output through coordinated switching. This segmentation reduces the complexity of each individual unit while maintaining the benefits of multi-level topology for loss reduction and efficiency improvement.
2Loss of energy
If a four-level topology is used to achieve multi-level output, then circuit loss is reduced, but the quantity of bus capacitor groups increases and voltage equalization control becomes more complex
Solution Approach 1:
The patent merges the capacitor requirements of multiple three-level circuit units by connecting their capacitor groups in parallel. Instead of requiring separate capacitor groups for each level as in traditional multi-level topologies, the parallel connection of three-level units allows shared capacitor resources. The bus capacitors of different units are connected to common DC bus lines, reducing the total quantity of capacitor groups needed while maintaining the energy loss reduction benefits of multi-level operation.
3Loss of energy
If a four-level topology is used to reduce circuit loss, then efficiency is improved, but semiconductor devices require high voltage withstand capability (e.g., 1200V for 220V output)
Solution Approach 1:
The patent segments the voltage stress distribution by dividing the power conversion function across multiple three-level circuit units. Each unit's semiconductor devices only need to withstand the voltage required for three-level operation rather than the full multi-level voltage. The coordinated switching of parallel units achieves higher output levels without proportionally increasing the voltage stress on individual devices, thereby reducing the required voltage withstand capability while maintaining efficiency improvements.
4Adaptability or versatility
If a large quantity of bus capacitor groups are used in multi-level circuits, then multi-level output is achieved, but design complexity and component stress increase
Solution Approach 1:
The patent makes the three-level circuit units universal and reusable by designing them with standardized capacitor groups and switching structures. Each unit can function independently or in combination with other identical units. The same three-level circuit unit design can be replicated and connected in parallel to achieve different multi-level configurations (five-level, seven-level, or higher), reducing design complexity through standardization and reusability while maintaining adaptability for various multi-level output requirements.
Data Source
Figure 1
Figure 2
Figure 3
AI summary
A multi-level circuit, a three-phase multi-level circuit, and a control method are provided. The multi-level circuit includes two groups of bus capacitors (C1 and C2) that are connected in series; a plurality of switching transistor branches that are connected in parallel to the capacitors, where each switching transistor branch includes a first half bridge (Q1 and Q2) and a second half bridge (Q3 and Q4), and a common terminal of the two half bridges is grounded (N); and two negative coupled inductors (L1 and L2), where each input terminal of each negative coupled inductor is connected to a common terminal (A1 and A2) of two switching transistors in the first half bridge in only one of the switching transistor branches. In this circuit, a quantity of groups of bus capacitors is decreased and circuit design complexity is reduced. Further, a dropout voltage of the switching transistors is reduced, and a component with a relatively low voltage withstand grade can be used in the circuit.