Multi-Level Contact IC Packaging for Thinner Profiles
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Solution Overview
Problem
Existing integrated circuit packaging technologies struggle to reduce package size, cost, and manufacturing time while maintaining performance and reliability, as they often require additional substrates that increase thickness and complexity.
Innovation Solution
The method involves forming multiple levels of contacts on external connection levels, attaching devices and connectors, and encapsulating them to create a thinner profile, utilizing existing manufacturing processes and eliminating the need for additional substrates, thereby reducing package size and cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional substrate material is used to support integrated circuit devices, then device reliability and connection stability are improved, but package thickness and manufacturing cost increase
Solution Approach 1:
The patent transitions from a planar substrate-based packaging architecture to a three-dimensional stacked architecture with multiple connection levels. Devices are arranged in vertical stacks with connection levels at different heights, enabling connections to be made in multiple dimensions rather than requiring a large flat substrate. This dimensional change reduces the horizontal footprint and allows for thinner overall package profiles while maintaining reliable connections through the stacked structure.
Solution Approach 2:
The patent implements a nested structure where multiple connection levels are integrated within a compact vertical stack. Connection levels are positioned at different heights and nested within the same package volume, with lower connection levels supporting upper levels. This nesting approach allows multiple connection functions to be packed into a small space without requiring additional substrate area, thereby reducing package thickness while maintaining connection reliability.
2Ease of manufacture
If traditional substrate-based packaging is used, then manufacturing processes are well-established and reliable, but package size and manufacturing cycle time increase
Solution Approach 1:
The patent merges multiple packaging functions into an integrated stacked structure. Connection levels, device mounting areas, and interconnection pathways are combined into a single three-dimensional architecture rather than being separate substrate layers. This consolidation reduces the number of discrete manufacturing steps and materials required, shortening the manufacturing cycle time while maintaining ease of manufacture through adapted existing processes for forming conductive structures and attaching devices.
Solution Approach 2:
The patent segments the package into discrete modular connection levels and device stacks that can be independently formed and then integrated. Each connection level can be prepared and tested separately before final assembly, enabling parallel processing and reducing overall manufacturing cycle time. This segmentation allows for more efficient production scheduling and reduces bottlenecks associated with traditional sequential substrate-based packaging processes.
3Ease of manufacture
If existing manufacturing methods are reused, then manufacturing cost is reduced, but package size cannot be effectively reduced
Solution Approach 1:
The patent applies existing manufacturing methods to create a three-dimensional stacked architecture instead of a planar layout. By utilizing vertical space and creating multiple connection levels at different heights, the design achieves higher device density within the same footprint without requiring new manufacturing equipment or processes. This dimensional transition allows cost-effective production of smaller packages using adapted existing tools and techniques.
Solution Approach 2:
The patent changes the geometric parameters of the package architecture from two-dimensional planar dimensions to three-dimensional stacked dimensions. By adjusting the vertical spacing between connection levels and optimizing the height of each stack, the package volume is reduced while maintaining manufacturing compatibility with existing processes. This parameter optimization enables size reduction without incurring the costs associated with developing entirely new manufacturing methodologies.
Data Source
AI summary
A method of manufacture of an integrated circuit packaging system includes: forming a first level contact on a first external connection level; forming a second level contact on a second external connection level next to the first external connection level; attaching a device adjacent the first level contact and the second level contact; attaching a first level device connector to the first level contact and the device; attaching a second level device connector to the second level contact and the device; and forming an encapsulant over the first level contact, the second level contact, the first level device connector, and the second level device connector.