Multi-level Data Encoding for High-Speed Transfer
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Solution Overview
Problem
Current data transfer methods such as SDR, DDR, and QDR are limited in their ability to efficiently transfer data, as they either transfer one, two, or four bits per clock cycle, with QDR requiring multiple data transitions per cycle, which can be inefficient and complex.
Innovation Solution
The proposed solution involves encoding two or more bits into one of several data states, allowing for the transfer of multiple bits per clock cycle while minimizing signal transitions, thereby achieving higher data rates like Quad Data Rate without the need for multiple transitions per cycle.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If QDR transfers data at four different points in the clock cycle, then data transfer rate increases, but signal transition complexity increases
Solution Approach 1:
The patent applies parameter changes by encoding multiple data bits into different states of a single signal parameter (voltage level) rather than using multiple signal transitions. Specifically, it uses multi-level voltage encoding where different voltage levels represent different data combinations, achieving high data transfer rates while maintaining simple single-edge clock transitions.
Solution Approach 2:
The patent transitions from the time dimension (multiple transitions per clock cycle) to the amplitude dimension (multiple voltage levels per transition). By encoding data in the voltage level rather than the number of transitions, it achieves QDR performance without the complexity of multiple clock edges or transitions.
2Productivity
If multiple data transitions are used per clock cycle to increase data rate, then productivity improves, but reliability decreases due to transition overhead
Solution Approach 1:
The patent changes the signaling parameter from transition-based (edge-triggered) to level-based (voltage-state). By using multi-level voltage encoding where the data is represented by the voltage level itself rather than transitions, it reduces signal stability issues while maintaining high data rates.
Solution Approach 2:
The patent extracts the data information from the transition events and places it in the signal level states. Instead of encoding data in the occurrence of transitions (which causes reliability issues), it encodes data in the sustained voltage levels between transitions, removing the harmful dependency on precise transition timing.
3Productivity
If data is encoded into time intervals of the clock cycle, then data transfer efficiency improves, but device complexity increases
Solution Approach 1:
The patent changes the encoding approach from time-based (which interval of the clock cycle) to amplitude-based (which voltage level). This parameter substitution simplifies the encoding logic while achieving the same data transfer efficiency, as voltage level comparison is simpler than time interval measurement and synchronization.
Data Source
AI summary
Multi-level encoded data transfer is disclosed. 2n bits may be encoded in a data signal each half clock cycle. For example, four bits may be transferred each clock cycle. Prior to data transfer, each data line may have two bits ready to be encoded. The two bits may be encoded to one of four different data states. The clock may be divided into four intervals for each half clock cycle, with each interval corresponding to one of the four data states. The two bits may be encoded into the data signal based on the interval that corresponds to the data state. As one example, the data signal could transition during the interval that corresponds to the data state for the two bits. This encoding may be repeated for two other bits for the other half of the clock cycle. Thus, QDR or some other data rate may be achieved.