Multi-Level ECC Decoder for Low Latency SSD Reads

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

Storage devices face latency issues due to the time-consuming process of error correction on large data units, which delays read requests, especially in applications like Deep Learning Recommendation Models that require rapid data retrieval.

Innovation Solution

Implementing a multi-level ECC decoder architecture that performs error correction on smaller data chunks rather than entire blocks, allowing for faster processing and reduced latency in read requests.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If error correction is performed on entire 4 KB blocks, then data reliability is improved, but read latency increases significantly

Engineering Contradiction:

Improvedata reliabilityVSAvoidread latency

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent segments the 4 KB data block into smaller 512-byte chunks, each with its own ECC codeword. This allows the system to perform error correction on smaller units independently, reducing the time required for read operations while maintaining overall data reliability through distributed error correction across multiple chunks.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent applies partial error correction by only correcting errors in the specific 512-byte chunks where errors are detected, rather than re-processing the entire 4 KB block. This partial action approach reduces unnecessary processing time while still ensuring data integrity where needed.

Inventive Principle:

Principle #16Partial or excessive action

2Loss of time

If error correction is performed on smaller 512-byte chunks, then read latency is reduced, but the complexity of the ECC decoding system increases

Engineering Contradiction:

Improveread latencyVSAvoidECC decoder complexity

Core Design Contradiction:

Loss of timeVSDevice complexity

Solution Approach 1:

The ECC decoder is segmented into multiple independent decoders, each handling a specific 512-byte chunk. This segmentation allows parallel processing of error correction across different chunks, reducing overall decoding time while distributing the computational complexity across multiple simpler decoder units rather than one complex decoder.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Each 512-byte chunk contains both data and its corresponding ECC codeword, creating a universal structure that can be processed independently. This multi-functional design allows the same decoder architecture to handle error correction for any chunk size, simplifying the overall system design while enabling fast processing through parallelization.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS12067254B2Low latency SSD read architecture with multi-level error correction codes (ECC)

Publication Date: 2024.08.20 SAMSUNG ELECTRONICS CO LTD

AI summary

A storage unit is disclosed. The storage unit may include storage for a component codeword. The component codeword may be stored in a block in the storage. The block may also store a block codeword. An interface may receive a read request for a chunk of data from a host and may send the chunk of data to the host. A circuit may read the component codeword from the block in the storage. An error correcting code (ECC) decoder may determine the chunk of data based at least in part on the component codeword.