Multi-Level Fuse Array Layout to Resist Reverse Engineering
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Solution Overview
Problem
Competitors can reverse engineer semiconductor devices by identifying the state of fuses in the interconnect structure, compromising the manufacturer's competitive edge and intellectual property.
Innovation Solution
Incorporating fuses at multiple conductive levels within the interconnect structure and omitting conductive elements randomly or in patterns to confuse the identification of effective and dummy fuses, thereby complicating reverse engineering.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If fuses are incorporated in a single conductive level, then the manufacturing process is simpler and production efficiency is higher, but the device becomes vulnerable to reverse engineering
Solution Approach 1:
The patent extends the fuse array from a single conductive level to multiple conductive levels (e.g., first and second conductive levels). This dimensional expansion complicates reverse engineering because competitors must analyze multiple layers to identify effective fuses, while manufacturing remains feasible using standard multi-level interconnect processes
Solution Approach 2:
The fuse array is segmented across different conductive levels, with effective fuses and dummy fuses distributed throughout the structure. This segmentation hides the functional significance of individual fuses, making it difficult for reverse engineers to determine which fuses actually control device functionality
2Object-affected harmful factors
If conductive elements are omitted to create dummy fuses, then reverse engineering difficulty increases, but the interconnect structure complexity increases
Solution Approach 1:
The patent creates dummy fuses by omitting conductive elements that would normally connect to other interconnect structures. These dummy fuses are copies of the effective fuse structure (with fuse material and surrounding dielectric) but lack the functional conductive connections. This copying approach increases reverse engineering difficulty without requiring fundamentally new manufacturing processes
Solution Approach 2:
Different regions of the interconnect structure have different qualities: effective fuses have complete conductive paths while dummy fuses have interrupted paths. This local variation in connectivity quality allows the structure to maintain overall simplicity while creating specific zones that complicate reverse engineering analysis
3Object-affected harmful factors
If multiple conductive levels with fuses are used, then reverse engineering difficulty increases, but manufacturing complexity and production time increase
Solution Approach 1:
The patent utilizes the vertical dimension by placing fuses across multiple conductive levels. This approach increases reverse engineering difficulty because competitors must grind through multiple layers to access and analyze fuses, thereby protecting intellectual property without fundamentally altering horizontal manufacturing workflows
Solution Approach 2:
The multi-level fuse array structure serves multiple functions: it provides the standard fuse functionality for device configuration while simultaneously acting as an anti reverse-engineering measure. The same structural elements (fuses, dielectric, conductive materials) perform both the configuration function and the security function, maintaining production efficiency
Data Source
AI summary
A method of making a semiconductor device includes electrically connecting a component to a first side of a first fuse, wherein the first fuse is a first distance from the component. The method further includes electrically connecting the component to a first side of a second fuse, wherein the second fuse is a second distance from the component, and the second distance is different than the first distance. The method further includes electrically connecting a second side of the second fuse to a dummy vertical interconnect segment.