Multi-Level Hash Tables for FPGA Throughput

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Solution Overview

Problem

Field Programmable Gate Arrays (FPGAs) have limited throughput in hash table operations due to small memory blocks and clock frequency limitations, which restricts the number of data entries that can be processed per clock cycle.

Innovation Solution

The implementation of multi-level hash tables (MHTs) and nested multi-level hash tables (NMHTs) in FPGAs, where multiple hash functions are used to distribute keys across multiple buffers and storage destinations, allowing for parallel processing and increased throughput by exploiting the parallel computation capabilities of FPGAs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If hash tables are built in FPGA memory blocks, then storage capacity is improved, but throughput is limited by clock frequency

Engineering Contradiction:
Improvestorage capacityVSAvoidthroughput
Core Design Contradiction:
Quantity of substanceVSProductivity

Solution Approach 1:

The hash table is divided into multiple levels (top-level, middle-level, bottom-level hash tables) with multiple buckets at each level. This segmentation allows parallel processing of multiple keys simultaneously across different buckets, overcoming the throughput limitation imposed by single-clock-cycle operations in FPGA memory blocks.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a multi-level hierarchical structure adding depth dimension to the traditional single-level hash table. Keys are distributed across multiple levels and buckets, enabling parallel computation paths and increasing throughput by processing multiple keys in parallel rather than sequentially within a single clock cycle.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Productivity

If multiple hash functions are used to distribute keys across multiple buffers, then throughput is improved, but device complexity increases

Engineering Contradiction:
ImprovethroughputVSAvoiddevice complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The system is segmented into distinct functional components: top-level hash tables for initial key distribution, middle-level hash tables for further distribution, bottom-level hash tables for final storage, and input buffers for key reception. Each component uses simplified hash functions appropriate to its level, reducing individual complexity while achieving high overall throughput through coordinated parallel operation.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS10346475B2Hash table structures
Publication Date: 2019.07.09 INTERNATIONAL BUSINESS MACHINE CORPORATION
  • US10346475B2 patent drawing
  • US10346475B2 patent drawing
  • US10346475B2 patent drawing

AI summary

Described herein are hash table structures and system and methods for creating and storing data in the hash table structures. Hash tables and input buffers associated with same are configured in several arrangements, including multi-level hash tables and nested multi-level hash tables. The hash table structures described herein are well suited for being configured in the memory blocks of field-programmable gate arrays.