Multi-Level On-Chip Inductor With Extending Conductive Lines
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Solution Overview
Problem
Conventional on-chip inductors face challenges in meeting various circuit-design demands due to limited adjustability of inductance and coupling parameters, as the location for connecting the innermost coil and branch structure is restricted within a small area.
Innovation Solution
The semiconductor device features a multi-level structure with winding portions and extending conductive lines arranged in a helix or spiral configuration, allowing for increased inductance and tuning range by separating the third extending conductive line and winding portions across different levels, and adjusting the overlap of conductive lines to control coupling parameters.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the location for connecting the innermost coil and branch structure is restricted within a small area, then the device complexity is reduced, but the adaptability for meeting various circuit-design demands deteriorates
Solution Approach 1:
The patent introduces a multi-level vertical structure with conductive lines at different heights (first level and second level), transforming the conventional planar inductor into a three-dimensional configuration. This dimensional change allows the extending conductive lines to connect to multiple winding portions without increasing the planar footprint, thereby improving circuit-design adaptability while maintaining compact device complexity
Solution Approach 2:
The inductor is segmented into multiple independent winding portions (first winding portion, second winding portion, third winding portion) located at different levels and positions. Each winding portion can be independently connected to extending conductive lines, allowing flexible configuration of inductance values and coupling parameters to meet various circuit-design demands
2Adaptability or versatility
If multi-level structure with extending conductive lines is introduced, then the adaptability for tuning inductance and coupling parameters is improved, but the device complexity increases
Solution Approach 1:
The patent utilizes vertical stacking of conductive lines at different levels (first level and second level) to create a three-dimensional inductor structure. This allows extending conductive lines to access multiple winding portions without expanding the planar area, enabling wide inductance tuning range while controlling device complexity through efficient space utilization
Solution Approach 2:
The extending conductive lines serve multiple functions: they connect different winding portions, enable tuning of inductance values, and control coupling parameters between windings. This multi-functionality reduces the need for separate adjustment mechanisms, improving adaptability while managing device complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances the flexibility of on-chip inductors by increasing inductance without area expansion, improving circuit design capabilities and expanding operable frequency ranges.
Implementation Method 1
A first winding portion and a second winding portion, which are electrically connected to the first winding portion, are disposed in a first level of the insulating layer and surround the center region. Each of the first winding portion and the second winding portion includes a plurality of conductive lines arranged from the inside to the outside.
Data Source
AI summary
A semiconductor device includes an insulating layer disposed over a substrate, wherein the insulating layer has a center region. A first winding portion and a second winding portion are electrically connected to the first winding portion, disposed in a first level of the insulating layer and surrounding the center region, wherein each of the first winding portion and the second winding portion comprises a plurality of conductive lines arranged from the inside to the outside. A first extending conductive line and a second extending conductive line partially surround the first extending conductive line, and are disposed in the first level of the insulating layer, wherein the first winding portion and the second winding portion surround the first extending conductive line and the second extending conductive line. A third extending conductive line is disposed in a second level of the insulating layer and surrounding the center region.