Multi-Level Instruction Scheduling in Microprocessor
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Solution Overview
Problem
Conventional instruction scheduling methods, such as in-order and out-of-order scheduling, face challenges in achieving optimal performance due to limitations in scheduler depth and the associated performance penalties, particularly in avoiding stalls caused by structural or data hazards.
Innovation Solution
The implementation of multi-level instruction scheduling using a scheduler circuit with a scheduling group circuit, a first selection circuit, and a second selection circuit, which writes scheduling entries in-order and selects ready entries based on group age information to optimize the selection process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If out-of-order scheduling is used to avoid stalls and improve performance, then microprocessor performance is improved, but hardware complexity increases due to additional comparisons needed to select instructions from a larger group
Solution Approach 1:
The patent divides the scheduling process into two hierarchical levels: a first selection circuit that performs initial filtering of ready instructions, and a second selection circuit that performs final selection from the filtered set. This segmentation reduces the complexity of the second selection circuit by limiting its input scope, while still enabling out-of-order execution from a large scheduler depth buffer.
Solution Approach 2:
The patent introduces a two-dimensional selection approach where instructions are selected based on both readiness status (first dimension) and selection priority (second dimension). The first selection circuit evaluates readiness across all instructions, while the second selection circuit evaluates priority among ready instructions, creating a dimensional hierarchy that manages complexity.
2Productivity
If scheduler depth is increased to reduce stalling probability, then performance advantage of out-of-order scheduling is improved, but the time required for performing comparisons increases and may compromise performance
Solution Approach 1:
The selection process is segmented into two stages: first selection circuit performs initial filtering to identify ready instructions, and second selection circuit performs final selection. This segmentation reduces the comparison time by dividing the workload, allowing larger scheduler depth without proportionally increasing total comparison time.
Solution Approach 2:
The first selection circuit performs preliminary action by pre-identifying ready instructions before the second selection circuit performs the final selection. This preliminary filtering reduces the number of instructions that need to be evaluated in the second stage, thereby reducing the time penalty associated with larger scheduler depth.
Data Source
AI summary
Aspects disclosed in the detailed description include multi-level instruction scheduling in a processor. Related methods and systems are also disclosed. In one exemplary aspect, an apparatus is provided that comprises a scheduler circuit comprising a scheduling group circuit, a first selection circuit, and a second selection circuit. The scheduling group circuit comprising a plurality of groups of scheduling entries, each scheduling entry among the groups of scheduling entries each comprising an instruction portion and a ready portion, each group configured to have its scheduling entries written in-order. The scheduling group circuit is further configured to maintain group age information associated with each group of the plurality of groups. The first selection circuit is configured to select a first in-order ready entry from each group. The second selection circuit is configured to select the first in-order ready entry belonging to the oldest group based on the group age information for scheduling.