Multi-Level Interconnect Via Formation via Selective Deposition
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Solution Overview
Problem
Designing viable integration processes for forming interconnection structures with multi-level vias remains a challenge, as conventional methods are inefficient and prone to irregular via structures and voids, especially in advanced technology nodes with tight pitch requirements.
Innovation Solution
A method for forming a multi-level interconnect structure that involves etching a multi-level via hole through the third and second dielectric layers, self-aligned with the first dielectric layer trench, using a trench mask and via mask, and selectively depositing conductive material to achieve a high-aspect ratio via with low resistance, reducing the need for planarization and minimizing voids.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional dual damascene process is used to form multi-level vias, then the process is simple and well-established, but it is inefficient and prone to irregular via structures and voids
Solution Approach 1:
The method performs preliminary actions by first forming the via hole through all dielectric layers before depositing any conductive materials. The via hole is etched to the required depth exposing the underlying conductive structure, and a seed layer is deposited beforehand to prepare the surface for subsequent conductive material deposition. This preliminary preparation prevents irregular via structures and voids that occur in conventional methods where via formation is done incrementally.
2Area of stationary object
If multi-level vias are formed with high aspect ratios, then area efficiency is improved and fewer intermediate islands are needed, but the process becomes more complex and difficult to control
Solution Approach 1:
The process segments the formation of multi-level vias into distinct sequential steps: (1) forming the via hole through all dielectric layers to the target conductive structure, (2) depositing a seed layer in the via hole, (3) selectively depositing conductive material in the via hole, and (4) filling trenches with conductive material. This segmentation allows precise control over each step, making high aspect ratio via formation manageable despite the complexity.
Solution Approach 2:
The method employs parameter changes by using selective deposition processes that control where conductive material is deposited based on material properties and process parameters. The selective deposition in via holes versus trenches is achieved by controlling deposition conditions, and the etch selectivity between dielectric layers and mask materials is optimized to achieve the desired via hole geometry with high aspect ratios.
3Ease of manufacture
If conventional via formation methods are used, then the process is easier to implement, but intermediate islands are required which reduce area efficiency
Solution Approach 1:
The method merges the formation of multi-level vias that bypass intermediate levels into a single integrated process. Instead of forming separate via holes at each level and requiring intermediate landing pads (islands), the process creates direct through-vias that connect non-adjacent interconnection levels. This merging eliminates the need for intermediate islands, improving area efficiency while maintaining process feasibility through systematic process integration.
4Manufacturing precision
If selective deposition is used to fill via holes, then voids are minimized and via quality is improved, but the deposition process becomes more complex
Solution Approach 1:
The process uses a seed layer as an intermediary between the via hole wall and the conductive material to be deposited. The seed layer is first deposited conformally in the via hole, providing a nucleation surface that facilitates subsequent conductive material deposition. This intermediary layer ensures complete and void-free filling of high aspect ratio via holes while enabling control over the deposition process through the seed layer's material properties and thickness.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables reliable and efficient formation of multi-level vias with high aspect ratios and low resistance, reducing the need for intermediate 'islands' and enhancing area efficiency in dense circuitry, particularly beneficial for technology nodes with conductive line pitches below 40 nm.
Implementation Method 1
forming a multi-level via hole by etching the third dielectric layer in said region exposed within one of said trenches, wherein the multi-level via hole is formed by transferring said opening in the via mask into the third and second dielectric layers by etching
Implementation Method 2
selectively depositing a first conductive material in the multi-level via hole on said structure of the first set of conductive structures
Data Source
Figure 1a
Figure 1b~1c
Figure 1d~1e
AI summary
According to an aspect of the present inventive concept there is provided a method for forming a multi-level interconnect structure on a substrate, the method comprising: forming on the substrate a first interconnection level comprising a first dielectric layer and a first set of conductive structures arranged in the first dielectric layer, forming on the first interconnection level a second interconnection level comprising a second dielectric layer and a second set of conductive structures arranged in the second dielectric layer, forming on the second interconnection level a third interconnection level, wherein forming the third interconnection level comprises: forming a third dielectric layer, forming a trench mask on the third dielectric layer, the trench mask comprising a pattern of trenches for defining positions of a third set of conductive structures to be formed in the third dielectric layer, forming a multi-level via hole by etching the third dielectric layer in a region exposed within one of said trenches, said multi-level via hole extending through the third dielectric layer and the second dielectric layer to a structure of the first set of conductive structures such that a surface of said structure is exposed at a bottom of the multi-level via hole, selectively depositing a first conductive material in the multi-level via hole on said structure of the first set of conductive structures, transferring the pattern of the trench mask into the third dielectric layer by etching to form a set of dielectric layer trenches for accommodating the third set of conductive structures, and depositing a second conductive material filling said set of dielectric layer trenches, wherein the second conductive material deposited in one of the dielectric layer trenches is deposited on said first conductive material selectively deposited in the multi-level via hole.