Multi-Level Inverter PWM Generation Using DSP Segmentation
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Solution Overview
Problem
Conventional DSP chips are insufficient for generating PWM pulses for multi-level inverters with more than three levels, as they require all PWM peripheral units to output pulses, limiting the increase in inverter levels and causing a shortage of DSP peripheral units.
Innovation Solution
A method and device using only three PWM peripheral units of a DSP control unit to output PWM high frequency signals, which are sent to a detection control unit to determine high frequency complementary switches based on level signals from GPIO interfaces, distributing the signals effectively between two switches while maintaining other switches unchanged, thereby reducing the number of DSP peripheral units needed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If all PWM peripheral units of the DSP chip are used to output PWM pulses for a three-phase three-level inverter, then the PWM pulse output requirement is met, but the inverter level cannot be increased due to shortage of PWM peripheral units
Solution Approach 1:
The invention segments the PWM pulse generation function into two parts: (1) The DSP chip generates only the triangular carrier wave and basic control signals using minimal PWM peripheral units (only 3 units for 3-phase), and (2) The inverter control unit (separate from DSP) generates the actual PWM pulses by combining the carrier wave with level signals from GPIO interfaces. This segmentation allows the system to support higher level inverters without requiring proportional increases in DSP PWM peripheral units.
Solution Approach 2:
The invention introduces an intermediary inverter control unit that acts as a bridge between the DSP chip and the inverter switches. This control unit receives the triangular carrier wave from the DSP and level signals from GPIO interfaces, then generates the PWM pulses by comparing these inputs. This intermediary handles the complex PWM generation logic externally, freeing the DSP's PWM peripheral units for other uses while enabling support for higher level inverters.
2Productivity
If the number of levels of the inverter is increased to five levels with 24 switches, then the inverter performance is improved, but the DSP chip cannot output sufficient PWM pulses due to limited PWM peripheral units
Solution Approach 1:
The invention makes the inverter control unit universal by designing it to handle PWM generation for inverters of any level (3-level, 5-level, or higher) using the same basic mechanism. The control unit universally compares the triangular carrier wave with level signals from GPIO interfaces to generate PWM pulses, regardless of the specific number of levels. This universal approach allows a single control unit design to support high-performance multi-level inverters without requiring additional DSP PWM peripheral units.
3Reliability
If conventional DSP chips are used to generate PWM pulses for multi-level inverters, then the control function is achieved, but the shortage of DSP peripheral units limits further increases in inverter levels
Solution Approach 1:
The invention extracts the PWM pulse generation function from the DSP chip and relocates it to a separate inverter control unit. The DSP chip retains only the essential functions of generating the triangular carrier wave and reading level signals from GPIO interfaces. The complex PWM generation logic is taken out and implemented externally, allowing the system to maintain reliable control while gaining the ability to support higher level inverters that would otherwise exceed the DSP's PWM peripheral unit capacity.
Data Source
AI summary
A method and a device for generating PWM pulses for an inverter are provided. The three-phase inverter's characteristic of including high frequency complementary switches is used. Only three PWM peripheral units of a DSP control unit are used to output PWM high frequency signals, and a detection control unit determine for each phase two currently high frequency complementary switches according to the states of detected level signals outputted by a preset number of GPIO interfaces. The PWM high frequency signals are distributed for each phase to one of the two switches, and the PWM high frequency signals are inversed and then sent to the other one of the two switches. In addition, the states of other switches are maintained unchanged according to a preset correspondence between states of switches of a multi-level inverter and outputted level signals in different switching periods.