Multi-level inverter synchronous rectification power loss
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Solution Overview
Problem
Existing multi-level inverters suffer from high conduction losses and low conversion efficiency due to high switch losses and power consumption, particularly in switch units with high on-state voltage drops, which limits their switch frequency and increases harmonic components in output voltages.
Innovation Solution
The proposed multi-level inverter design incorporates switch transistors with anti-parallel diodes, reducing power loss by using switch transistors with small on-state resistance and connecting them in a configuration that minimizes power consumption, including an energy storage inductor and capacitor in series within the filtering circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If diodes with high on-state voltage drop are used in the inverter circuit, then the circuit structure can be simplified, but the conduction loss increases significantly
Solution Approach 1:
The patent changes the key parameter from diode on-state voltage drop to switch on-state resistance. By using switches with small on-state resistance instead of diodes with high on-state voltage drop, the invention reduces conduction loss while maintaining circuit simplicity. The switch units are configured to conduct during specific time periods, optimizing the resistance characteristics.
Solution Approach 2:
The patent introduces dynamic switching control where switch units are turned on and off at different time periods. This dynamic operation allows the circuit to use low-resistance paths when needed, reducing conduction loss compared to static diode-based solutions. The control circuit dynamically adjusts which switches conduct based on operating conditions.
2Manufacturing precision
If switch frequency is increased to improve PWM performance, then output voltage quality improves, but switch loss increases
Solution Approach 1:
The patent changes the critical parameter from switch voltage stress to switch on-state resistance. By selecting switches with small on-state resistance, the invention enables higher switching frequencies with acceptable loss levels. The multi-level topology also reduces the voltage stress on individual switches, further enabling high-frequency operation.
Solution Approach 2:
The patent segments the voltage stress across multiple switch units in a multi-level configuration. Instead of one switch handling the full bus voltage, multiple switches share the voltage stress, allowing each switch to operate at lower voltage levels and reducing switching losses. This segmentation enables higher overall switching frequencies.
3Device complexity
If two-level or three-level inverters are used to reduce implementation complexity, then the circuit is easier to implement, but output voltage has high harmonic components
Solution Approach 1:
The patent segments the output voltage into multiple levels (five-level operation) by using multiple switch units connected in series between positive and negative direct current buses. This segmentation creates a stepped voltage waveform with fewer harmonics compared to two-level or three-level inverters, while keeping each individual switch unit relatively simple.
Solution Approach 2:
The patent adds a voltage level dimension by introducing multiple bus capacitors (first, second, third, fourth bus capacitors) connected in series between positive and negative direct current buses. This creates five distinct voltage levels (+Vbus, +0.5Vbus, 0, -0.5Vbus, -Vbus), transforming the output from a two-level or three-level waveform to a five-level waveform with superior harmonic characteristics.
4Strength
If high withstand voltage switch devices are selected for two-level inverters, then voltage stress is handled, but conduction loss increases due to higher resistance
Solution Approach 1:
The patent segments the high voltage stress across multiple switch units, each handling only a portion of the total bus voltage. This allows the use of switches with lower individual voltage ratings and lower on-state resistance, reducing conduction loss compared to using a single high-voltage switch with inherently higher resistance.
Solution Approach 2:
The patent changes the voltage stress parameter distribution from concentrated (single switch) to distributed (multiple switches in series). Each switch experiences reduced voltage stress, allowing selection of switches optimized for lower voltage and lower resistance, thereby reducing overall conduction loss in the circuit.
Data Source
AI summary
Provided is a multi-level inverter, which includes a first bus capacitor, a second bus capacitor, a third bus capacitor, a fourth bus capacitor, a seventh switch unit, an eighth switch unit, an inverter circuit and a filtering circuit. The first bus capacitor, the second bus capacitor, the third bus capacitor and the fourth bus capacitor are connected between a positive direct current bus and a negative direct current bus in series, and a series point between the second bus capacitor and the third bus capacitor is grounded. The switch transistor of the anti-parallel diode having small on-state resistance is used in the multi-level inverter, thereby reducing power loss of the switch unit in the multi-level inverter and reducing power consumption of the circuit.