Multi-Level Leadframe with Interconnect Areas for Stacked Packages
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Solution Overview
Problem
Conventional semiconductor package assemblies face challenges in achieving high packaging density and reliability due to large area occupation and adverse effects from reflow processes, particularly with side-by-side chip arrangements and complex bonding processes in stacked assemblies.
Innovation Solution
A leadframe design with grouped leads of varying heights and protrusion portions allows for stacked electronic device mounting, reducing the need for bonding wires and simplifying the manufacturing process by direct soldering to interconnect areas, while encapsulating to maintain electrical connectivity and reduce reflow-induced damage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If integrated circuit chips are arranged side by side on a leadframe, then electrical connections can be established between chips and leadframe, but the package assembly occupies a larger area reducing packaging density
Solution Approach 1:
The patent transitions from a two-dimensional side-by-side chip arrangement to a three-dimensional stacked arrangement. Multiple levels of leads with different heights enable chips to be stacked vertically, utilizing the vertical dimension to reduce the horizontal footprint of the package assembly while maintaining electrical connection reliability through multiple interconnect areas at different levels.
2Strength
If multiple reflow processes are performed to secure multiple chips, then chips can be firmly attached to the leadframe, but the repeated reflow may damage existing solder joints
Solution Approach 1:
The patent designs the leadframe with multiple interconnect areas at different heights before chip mounting. This preliminary structural preparation allows different chips to be mounted at different stages without requiring repeated reflow of existing joints, as each chip can be attached to its corresponding height level independently, thereby protecting existing solder joints from damage.
3Area of stationary object
If bonding wires are used to electrically couple chips in a stacked arrangement, then packaging density is improved, but the manufacturing process becomes more complex and costly
Solution Approach 1:
The patent merges the electrical connection function with the mechanical support structure by integrating multiple interconnect areas directly into the leadframe at different heights. This eliminates the need for separate bonding wires to establish electrical connections between stacked chips, thereby reducing manufacturing process complexity and cost while maintaining the space-efficient stacked arrangement.
4Productivity
If leads are grouped with interconnect areas at different heights, then stacked chip arrangement is enabled improving packaging density, but the leadframe structure becomes more complex
Solution Approach 1:
The patent segments the leadframe into multiple groups of leads, with each group having interconnect areas at different heights. This segmentation allows independent design and optimization of each lead group for specific stacking levels, making the overall complex structure manageable through modular organization while enabling high-density stacked chip arrangement.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances packaging density and reliability by minimizing bonding wire usage and simplifying the manufacturing process, reducing the adverse effects of reflow on electronic devices, and improving the overall reliability of the package assembly.
Implementation Method 1
A reflow process is performed so that the solder balls 122 are melted to form solders 122
Data Source
AI summary
A leadframe, a package assembly and methods for manufacturing the same are disclosed. A plurality of electronic devices are stacked in a plurality of levels in the package assembly. The leadframe includes a plurality of leads having interconnect areas. The plurality of leads are grouped so that the interconnect areas of each group of leads have a height corresponding to one level of electronic devices. In the package assembly, the interconnect areas of each group of leads are soldered to one level of electronic devices. The leadframe and the package assembly result in increased packaging density, less usage of bonding wires in the package assembly, and improve reliability. The method for manufacturing the package assembly reduces adverse effects of a reflow process on properties of the electronic devices, and thus further improves reliability of the package assembly.