Multi-Level Local Interconnect for High Density Transistor Layouts
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Solution Overview
Problem
In deep sub-micron semiconductor technology, the layout of local interconnects for blocking transistors is awkward, leading to decreased density and inefficiency due to the need for complex charging of gates, which complicates the layout and reduces the effectiveness of continuous diffusion regions in achieving adequate crystal lattice strain for transistor strength.
Innovation Solution
A multi-level local interconnect structure is introduced, comprising gate-directed and diffusion-directed local interconnects that allow for efficient coupling between gate layers and diffusion regions, enabling dense and area-efficient layouts by eliminating the need for overlapping interconnects and optimizing the placement of vias, thereby enhancing the density of transistor arrangements on continuous diffusion regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If continuous diffusion regions are used to achieve adequate crystal lattice strain for transistor strength, then transistor strength is improved, but the layout becomes complicated due to the need for blocking transistors and complex local interconnect charging
Solution Approach 1:
The patent introduces multi-level local interconnect structures that extend the interconnect architecture into the vertical dimension. By using multiple metal layers (M1, M2, M3) and via connections, the charging of blocking transistor gates is achieved through vertical stacking rather than horizontal routing, thereby reducing layout complexity while maintaining continuous diffusion regions for transistor strength
Solution Approach 2:
The patent employs intermediate structures such as dummy transistors and multi-level interconnect elements that act as mediators to simplify the charging of blocking transistor gates. These intermediaries provide systematic ways to distribute control signals without requiring complex direct routing to each blocking transistor, thus reducing overall layout complexity
2Reliability
If traditional local interconnect layouts are used for blocking transistors, then gate charging can be achieved, but density decreases due to awkward layout and overlapping interconnects
Solution Approach 1:
The patent resolves the density issue by moving interconnect routing from the horizontal plane to multiple vertical levels. The multi-level local interconnect structure allows gate charging functionality to be achieved through vertical stacking of metal layers and via connections, eliminating the need for overlapping interconnects in the horizontal plane and thereby increasing transistor density
3Reliability
If diffusion regions are extended to form continuous regions for increased local strain, then transistor performance is improved, but interconnect routing becomes more difficult due to space constraints
Solution Approach 1:
The patent addresses the interconnect routing difficulty by utilizing multiple metal layers and via connections to create vertical routing paths. This multi-level approach allows interconnects to bypass horizontal space constraints imposed by continuous diffusion regions, making routing easier while preserving the performance benefits of continuous diffusion regions for increased local strain
Data Source
Figure 1~2
Figure 3
Figure 4A~4B
AI summary
A local interconnect structure is provided that includes a gate- directed local interconnect (435) coupled to an adjacent gate layer (425) through a diffusion-directed local interconnect (445).