Multi-Level Memory Level Control via Centralized Controller
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Solution Overview
Problem
Existing multi-level nonvolatile memory technologies face challenges in accurately determining and maintaining optimal predefined levels due to variability in manufacturing and over time, leading to potential misreading and errors, which increases complexity and cost in memory chip fabrication and operation.
Innovation Solution
Relocating level control functionality from memory chips to a central memory controller, which determines and communicates optimal predefined levels and processes read measurements to extract valid data, reducing the need for complex fabrication and replicating firmware across multiple chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If level control functionality is integrated into memory chips, then data accuracy and reliability can be maintained at the chip level, but device complexity and fabrication costs increase significantly
Solution Approach 1:
The patent extracts the level control functionality from individual memory chips and relocates it to an external memory controller. The memory controller includes a level detector that monitors storage element levels and communicates optimal predefined levels back to the chips, separating the control logic from the storage elements and reducing chip complexity while maintaining data accuracy
Solution Approach 2:
The patent introduces an intermediary memory controller that acts as a mediator between the host system and multiple memory chips. This controller detects levels, determines optimal predefined levels, and manages the communication between chips and host, centralizing the complex level control functionality outside the chips themselves
2Measurement precision
If optimal predefined levels are determined and maintained at each memory chip, then data reading accuracy improves, but fabrication costs and manufacturing complexity increase
Solution Approach 1:
The patent merges the level detection and predefined level determination functionality into a single external memory controller that serves multiple chips. Instead of each chip having its own level control circuitry, the controller consolidates these functions, reducing per-chip fabrication costs while maintaining measurement precision through centralized monitoring and adjustment
Solution Approach 2:
The memory controller is designed as a universal device that can manage multiple memory chips, detecting levels and determining optimal predefined levels for all connected chips. This multi-functional approach eliminates the need for duplicate level control functionality in each chip, reducing manufacturing complexity and cost
3Ease of operation
If firmware is replicated across multiple memory chips, then each chip can operate independently with accurate level control, but device complexity and cost increase
Solution Approach 1:
The patent extracts the firmware-level control logic from individual chips and places it in an external memory controller. The controller maintains the predefined level information and level detection algorithms, allowing chips to operate independently for data storage while the controller handles the complex level management functions centrally
Solution Approach 2:
Instead of replicating complex level control firmware in each chip, the patent uses the memory controller to generate and communicate optimal predefined levels to multiple chips. The controller effectively copies the level control functionality to where it is needed, reducing the need for duplicate firmware in each chip
Data Source
AI summary
A memory chip includes a plurality of storage elements. A method of controlling the memory chip includes receiving a plurality of target values from a memory controller. Each target value of the plurality of target values received from the memory controller corresponds to a respective one of the plurality of storage elements. The method further includes, for each storage element of the plurality of storage elements, adjusting a measurable parameter of the storage element until the measurable parameter of the storage element reaches the target value corresponding to the storage element received from the memory controller.