Multi-Level Memory ECC Placement for Faster Reliable Programming
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Solution Overview
Problem
Traditional solid-state memory devices face inefficiencies in programming and reading operations due to their binary nature, which becomes cumbersome as more bits are stored per cell, leading to longer operation times and increased susceptibility to errors as the bits per cell count increases.
Innovation Solution
The memory devices utilize multi-level cells (MLCs) that store data as threshold voltage ranges, allowing for program and read operations to handle data signals as full representations of bit patterns rather than discrete bits, enabling a single operation to return multiple bits of information, and incorporate error correction code by varying the bit level per cell based on reliability characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple bits are stored on each multi-level cell, then storage capacity is improved, but operation time increases due to binary read/write limitations
Solution Approach 1:
The patent replaces the mechanical binary read/write operation system with an analog signal processing system. Instead of performing multiple sequential binary operations to read or write multi-bit data, the system uses analog voltage signals that directly represent the threshold voltage of memory cells, enabling single-operation read and write of multiple bits simultaneously.
Solution Approach 2:
The patent changes the parameter representation from discrete binary values to continuous analog voltage levels. By encoding multiple bits as different voltage levels (e.g., 0V for 00, 0.5V for 01, 1.0V for 10, 1.5V for 11), the system can store and retrieve multiple bits per cell while maintaining single-operation speed.
2Quantity of substance
If more bits are stored per cell, then storage density is improved, but error susceptibility increases due to binary operation limitations
Solution Approach 1:
The patent replaces error-prone binary operations with analog signal processing that inherently preserves data integrity. By reading the analog threshold voltage directly without multiple binary read cycles, the system eliminates cumulative errors that occur in traditional multi-bit binary operations.
3Device complexity
If traditional binary read/write operations are used, then device complexity is reduced, but productivity decreases due to multiple operations required per bit
Solution Approach 1:
The patent merges multiple binary read/write operations into a single analog operation. By combining the read or write of multiple bits into one simultaneous analog signal operation, the system achieves higher productivity without significantly increasing device complexity, as the analog signaling approach uses standard voltage levels and comparators.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces operation times and enhances reliability by allowing a single read operation to represent multiple bits of information and adaptively managing error correction based on cell reliability, thereby improving storage efficiency and accuracy.
Implementation Method 1
The memory devices utilize multi-level cells (MLCs) that store data as threshold voltage ranges
Data Source
AI summary
Memory devices that, in a particular embodiment, receive and transmit analog data signals representative of bit patterns of two or more bits such as to facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. Programming error correction code (ECC) and metadata into such memory devices includes storing the ECC and metadata at different bit levels per cell based on an actual error rate of the cells. The ECC and metadata can be stored with the data block at a different bit level than the data block. If the area of memory in which the block of data is stored does not support the desired reliability for the ECC and metadata at a particular bit level, the ECC and metadata can be stored in other areas of the memory array at different bit levels.